Merge branch 'master' of git://git.denx.de/u-boot-spi

[platform/kernel/u-boot.git] / arch / arm / dts / r8a7791.dtsi

diff --git a/arch/arm/dts/r8a7791.dtsi b/arch/arm/dts/r8a7791.dtsi
index d728738..991ac6f 100644 (file)
--- a/arch/arm/dts/r8a7791.dtsi
+++ b/arch/arm/dts/r8a7791.dtsi
@@ -75,11 +75,11 @@
                        compatible = "arm,cortex-a15";
                        reg = <0>;
                        clock-frequency = <1500000000>;
-                       voltage-tolerance = <1>; /* 1% */
                        clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
-                       clock-latency = <300000>; /* 300 us */
                        power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
                        next-level-cache = <&L2_CA15>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
 
                        /* kHz - uV - OPPs unknown yet */
                        operating-points = <1500000 1000000>,
@@ -98,6 +98,16 @@
                        clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
                        power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
                        next-level-cache = <&L2_CA15>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
+
+                       /* kHz - uV - OPPs unknown yet */
+                       operating-points = <1500000 1000000>,
+                                          <1312500 1000000>,
+                                          <1125000 1000000>,
+                                          < 937500 1000000>,
+                                          < 750000 1000000>,
+                                          < 375000 1000000>;
                };
 
                L2_CA15: cache-controller-0 {
@@ -123,6 +133,13 @@
                clock-frequency = <0>;
        };
 
+       pmu {
+               compatible = "arm,cortex-a15-pmu";
+               interrupts-extended = <&gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                                     <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+               interrupt-affinity = <&cpu0>, <&cpu1>;
+       };
+
        /* External SCIF clock */
        scif_clk: scif {
                compatible = "fixed-clock";
@@ -139,6 +156,16 @@
                #size-cells = <2>;
                ranges;
 
+               rwdt: watchdog@e6020000 {
+                       compatible = "renesas,r8a7791-wdt",
+                                    "renesas,rcar-gen2-wdt";
+                       reg = <0 0xe6020000 0 0x0c>;
+                       clocks = <&cpg CPG_MOD 402>;
+                       power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                       resets = <&cpg 402>;
+                       status = "disabled";
+               };
+
                gpio0: gpio@e6050000 {
                        compatible = "renesas,gpio-r8a7791",
                                     "renesas,rcar-gen2-gpio";
@@ -404,7 +431,7 @@
 
                        smp-sram@0 {
                                compatible = "renesas,smp-sram";
-                               reg = <0 0x10>;
+                               reg = <0 0x100>;
                        };
                };
 
@@ -1618,6 +1645,24 @@
                        resets = <&cpg 127>;
                };
 
+               fdp1@fe940000 {
+                       compatible = "renesas,fdp1";
+                       reg = <0 0xfe940000 0 0x2400>;
+                       interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 119>;
+                       power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                       resets = <&cpg 119>;
+               };
+
+               fdp1@fe944000 {
+                       compatible = "renesas,fdp1";
+                       reg = <0 0xfe944000 0 0x2400>;
+                       interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&cpg CPG_MOD 118>;
+                       power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+                       resets = <&cpg 118>;
+               };
+
                jpu: jpeg-codec@fe980000 {
                        compatible = "renesas,jpu-r8a7791",
                                     "renesas,rcar-gen2-jpu";