Merge tag 'u-boot-atmel-fixes-2021.01-b' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / arch / arm / dts / meson-g12b.dtsi

diff --git a/arch/arm/dts/meson-g12b.dtsi b/arch/arm/dts/meson-g12b.dtsi
index 5628ccd..9b8548e 100644 (file)
--- a/arch/arm/dts/meson-g12b.dtsi
+++ b/arch/arm/dts/meson-g12b.dtsi
@@ -4,8 +4,7 @@
  * Author: Neil Armstrong <narmstrong@baylibre.com>
  */
 
-#include "meson-g12-common.dtsi"
-#include <dt-bindings/power/meson-g12a-power.h>
+#include "meson-g12.dtsi"
 
 / {
        compatible = "amlogic,g12b";
@@ -49,7 +48,9 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x0>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <592>;
                        next-level-cache = <&l2>;
+                       #cooling-cells = <2>;
                };
 
                cpu1: cpu@1 {
@@ -57,7 +58,9 @@
                        compatible = "arm,cortex-a53";
                        reg = <0x0 0x1>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <592>;
                        next-level-cache = <&l2>;
+                       #cooling-cells = <2>;
                };
 
                cpu100: cpu@100 {
@@ -65,7 +68,9 @@
                        compatible = "arm,cortex-a73";
                        reg = <0x0 0x100>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        next-level-cache = <&l2>;
+                       #cooling-cells = <2>;
                };
 
                cpu101: cpu@101 {
@@ -73,7 +78,9 @@
                        compatible = "arm,cortex-a73";
                        reg = <0x0 0x101>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        next-level-cache = <&l2>;
+                       #cooling-cells = <2>;
                };
 
                cpu102: cpu@102 {
@@ -81,7 +88,9 @@
                        compatible = "arm,cortex-a73";
                        reg = <0x0 0x102>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        next-level-cache = <&l2>;
+                       #cooling-cells = <2>;
                };
 
                cpu103: cpu@103 {
@@ -89,7 +98,9 @@
                        compatible = "arm,cortex-a73";
                        reg = <0x0 0x103>;
                        enable-method = "psci";
+                       capacity-dmips-mhz = <1024>;
                        next-level-cache = <&l2>;
+                       #cooling-cells = <2>;
                };
 
                l2: l2-cache0 {
@@ -102,14 +113,25 @@
        compatible = "amlogic,g12b-clkc";
 };
 
-&ethmac {
-       power-domains = <&pwrc PWRC_G12A_ETH_ID>;
-};
-
-&vpu {
-       power-domains = <&pwrc PWRC_G12A_VPU_ID>;
-};
-
-&sd_emmc_a {
-       amlogic,dram-access-quirk;
+&cpu_thermal {
+       cooling-maps {
+               map0 {
+                       trip = <&cpu_passive>;
+                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                        <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                        <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                        <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                        <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                        <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+               };
+               map1 {
+                       trip = <&cpu_hot>;
+                       cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                        <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                        <&cpu100 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                        <&cpu101 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                        <&cpu102 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
+                                        <&cpu103 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+               };
+       };
 };