*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include "skeleton.dtsi"
/ {
model = "Texas Instruments K2G SoC";
#size-cells = <1>;
interrupt-parent = <&gic>;
+ chosen { };
+
aliases {
serial0 = &uart0;
spi0 = &spi0;
spi2 = &spi2;
spi3 = &spi3;
spi4 = &qspi;
- };
-
- memory {
- device_type = "memory";
- reg = <0x80000000 0x80000000>;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
};
cpus {
};
qspi: qspi@2940000 {
- compatible = "cadence,qspi";
+ compatible = "cdns,qspi-nor";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x02940000 0x1000>,
<0x24000000 0x4000000>;
interrupts = <GIC_SPI 198 IRQ_TYPE_EDGE_RISING>;
num-cs = <4>;
- fifo-depth = <256>;
- sram-size = <256>;
+ cdns,fifo-depth = <256>;
+ cdns,fifo-width = <4>;
+ cdns,trigger-address = <0x24000000>;
status = "disabled";
};
#size-cells = <0>;
status = "disabled";
};
+ i2c0: i2c@2530000 {
+ compatible = "ti,keystone-i2c";
+ reg = <0x02530000 0x400>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 88 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@2530400 {
+ compatible = "ti,keystone-i2c";
+ reg = <0x02530400 0x400>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@2530800 {
+ compatible = "ti,keystone-i2c";
+ reg = <0x02530800 0x400>;
+ clock-frequency = <100000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
mmc0: mmc@23000000 {
compatible = "ti,omap4-hsmmc";