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imx: sync with kernel device tree for Phycore SoM
[platform/kernel/u-boot.git] / arch / arm / dts / imx6ul-phytec-phycore-som.dtsi
diff --git a/arch/arm/dts/pcl063-common.dtsi b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
similarity index 56%
rename from arch/arm/dts/pcl063-common.dtsi
rename to arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
index b88dde2..c2a7c78 100644 (file)
--- a/arch/arm/dts/pcl063-common.dtsi
+++ b/arch/arm/dts/imx6ul-phytec-phycore-som.dtsi
@@ -1,22 +1,35 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: GPL-2.0
 /*
- * Copyright (C) 2018 Collabora Ltd.
- *
- * Based on dts[i] from Phytec barebox port:
  * Copyright (C) 2016 PHYTEC Messtechnik GmbH
  * Author: Christian Hemp <c.hemp@phytec.de>
  */
 
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/pwm/pwm.h>
+
 / {
-       model = "Phytec phyCORE-i.MX6 Ultra Lite SOM";
+       model = "PHYTEC phyCORE-i.MX6 UltraLite";
        compatible = "phytec,imx6ul-pcl063", "fsl,imx6ul";
 
+       chosen {
+               stdout-path = &uart1;
+       };
+
        memory {
+               device_type = "memory";
                reg = <0x80000000 0x20000000>;
        };
 
-       chosen {
-               stdout-path = &uart1;
+       gpio_leds_som: leds {
+               pinctrl-names = "default";
+               pinctrl-0 = <&pinctrl_gpioleds_som>;
+               compatible = "gpio-leds";
+
+               phycore-green {
+                       gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
+                       linux,default-trigger = "heartbeat";
+               };
        };
 };
 
@@ -24,16 +37,21 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_enet1>;
        phy-mode = "rmii";
-       phy-handle = <&ethphy0>;
-       status = "okay";
+       phy-handle = <&ethphy1>;
+       status = "disabled";
 
        mdio: mdio {
                #address-cells = <1>;
                #size-cells = <0>;
 
-               ethphy0: ethernet-phy@1 {
+               ethphy1: ethernet-phy@1 {
                        reg = <1>;
+                       interrupt-parent = <&gpio1>;
+                       interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
                        micrel,led-mode = <1>;
+                       clocks = <&clks IMX6UL_CLK_ENET_REF>;
+                       clock-names = "rmii-ref";
+                       status = "disabled";
                };
        };
 };
@@ -42,89 +60,61 @@
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_gpmi_nand>;
        nand-on-flash-bbt;
-       fsl,no-blockmark-swap;
        status = "disabled";
-
-       #address-cells = <1>;
-       #size-cells = <1>;
-
-       partition@0 {
-               label = "uboot";
-               reg = <0x0 0x400000>;
-       };
-
-       partition@400000 {
-               label = "uboot-env";
-               reg = <0x400000 0x100000>;
-       };
-
-       partition@500000 {
-               label = "root";
-               reg = <0x500000 0x0>;
-       };
 };
 
 &i2c1 {
-       clock-frequency = <100000>;
-       pinctrl-names = "default", "gpio";
+       pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_i2c1>;
-       pinctrl-1 = <&pinctrl_i2c1_gpio>;
-       scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
-       sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
+       clock-frequency = <100000>;
        status = "okay";
 
        eeprom@52 {
-               compatible = "cat,24c32";
+               compatible = "catalyst,24c32", "atmel,24c32";
                reg = <0x52>;
        };
 };
 
-&uart1 {
-       pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_uart1>;
+&snvs_poweroff {
        status = "okay";
 };
 
-&usdhc1 {
+&uart1 {
        pinctrl-names = "default";
-       pinctrl-0 = <&pinctrl_usdhc1>;
-       cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
-       bus-width = <0x4>;
-       pinctrl-0 = <&pinctrl_usdhc1>;
-       no-1-8-v;
+       pinctrl-0 = <&pinctrl_uart1>;
        status = "okay";
 };
 
 &usdhc2 {
-       u-boot,dm-spl;
-       u-boot,dm-pre-reloc;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_usdhc2>;
        bus-width = <8>;
        no-1-8-v;
        non-removable;
-       keep-power-in-suspend;
        status = "disabled";
 };
 
 &iomuxc {
-       pinctrl-names = "default";
-
        pinctrl_enet1: enet1grp {
                fsl,pins = <
-                       MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x1b0b0
-                       MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x1b0b0
+                       MX6UL_PAD_GPIO1_IO07__ENET1_MDC         0x10010
+                       MX6UL_PAD_GPIO1_IO06__ENET1_MDIO        0x10010
                        MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN      0x1b0b0
                        MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER      0x1b0b0
                        MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
                        MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
-                       MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b0b0
-                       MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
-                       MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
-                       MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b031
+                       MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN      0x1b010
+                       MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010
+                       MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010
+                       MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1  0x4001b010
+                       MX6UL_PAD_GPIO1_IO02__GPIO1_IO02        0x17059
                >;
        };
 
+       pinctrl_gpioleds_som: gpioledssomgrp {
+               fsl,pins = <MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04  0x0b0b0>;
+       };
+
        pinctrl_gpmi_nand: gpminandgrp {
                fsl,pins = <
                        MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0x0b0b1
@@ -147,35 +137,15 @@
 
        pinctrl_i2c1: i2cgrp {
                fsl,pins = <
-                       MX6UL_PAD_UART4_TX_DATA__I2C1_SCL       0x4001b8b0
-                       MX6UL_PAD_UART4_RX_DATA__I2C1_SDA       0x4001b8b0
-               >;
-       };
-
-       pinctrl_i2c1_gpio: i2c1grp_gpio {
-               fsl,pins = <
-                       MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
-                       MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
+                       MX6UL_PAD_UART4_TX_DATA__I2C1_SCL       0x4001b8b0
+                       MX6UL_PAD_UART4_RX_DATA__I2C1_SDA       0x4001b8b0
                >;
        };
 
        pinctrl_uart1: uart1grp {
                fsl,pins = <
-                       MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
-                       MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
-               >;
-       };
-
-       pinctrl_usdhc1: usdhc1grp {
-               fsl,pins = <
-                       MX6UL_PAD_SD1_CMD__USDHC1_CMD           0x17059
-                       MX6UL_PAD_SD1_CLK__USDHC1_CLK           0x10059
-                       MX6UL_PAD_SD1_DATA0__USDHC1_DATA0       0x17059
-                       MX6UL_PAD_SD1_DATA1__USDHC1_DATA1       0x17059
-                       MX6UL_PAD_SD1_DATA2__USDHC1_DATA2       0x17059
-                       MX6UL_PAD_SD1_DATA3__USDHC1_DATA3       0x17059
-                       MX6UL_PAD_UART1_RTS_B__GPIO1_IO19       0x17059
-
+                       MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX   0x1b0b1
+                       MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX   0x1b0b1
                >;
        };
 
@@ -191,7 +161,7 @@
                        MX6UL_PAD_NAND_DATA05__USDHC2_DATA5     0x170f9
                        MX6UL_PAD_NAND_DATA06__USDHC2_DATA6     0x170f9
                        MX6UL_PAD_NAND_DATA07__USDHC2_DATA7     0x170f9
-                       MX6UL_PAD_NAND_ALE__USDHC2_RESET_B      0x170f9
                >;
        };
+
 };
Domain: System / Kernel;