/*
* NXP lx2160a SOC common device tree source
*
- * Copyright 2018 NXP
+ * Copyright 2018-2020 NXP
*
*/
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
/ {
compatible = "fsl,lx2160a";
interrupt-parent = <&gic>;
interrupts = <1 9 0x4>;
};
+ gic_lpi_base: syscon@0x80000000 {
+ compatible = "gic-lpi-base";
+ reg = <0x0 0x80000000 0x0 0x200000>;
+ max-gic-redistributors = <16>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
<1 10 0x8>; /* Hypervisor PPI, active-low */
};
+ fspi: flexspi@20c0000 {
+ compatible = "nxp,lx2160a-fspi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x20c0000 0x0 0x10000>,
+ <0x0 0x20000000 0x0 0x10000000>;
+ reg-names = "fspi_base", "fspi_mmap";
+ clocks = <&clockgen 4 3>, <&clockgen 4 3>;
+ clock-names = "fspi_en", "fspi";
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
i2c0: i2c@2000000 {
compatible = "fsl,vf610-i2c";
#address-cells = <1>;
num-cs = <6>;
};
+ gpio0: gpio@2300000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2300000 0x0 0x10000>;
+ interrupts = <0 36 4>;
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ gpio1: gpio@2310000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2310000 0x0 0x10000>;
+ interrupts = <0 36 4>;
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
gpio2: gpio@2320000 {
compatible = "fsl,qoriq-gpio";
reg = <0x0 0x2320000 0x0 0x10000>;
#interrupt-cells = <2>;
};
+ gpio3: gpio@2330000 {
+ compatible = "fsl,qoriq-gpio";
+ reg = <0x0 0x2330000 0x0 0x10000>;
+ interrupts = <0 37 4>;
+ gpio-controller;
+ little-endian;
+ #gpio-cells = <2>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+
+ watchdog@23a0000 {
+ compatible = "arm,sbsa-gwdt";
+ reg = <0x0 0x23a0000 0 0x1000>,
+ <0x0 0x2390000 0 0x1000>;
+ timeout-sec = <30>;
+ };
+
usb0: usb3@3100000 {
compatible = "fsl,layerscape-dwc3";
reg = <0x0 0x3100000 0x0 0x10000>;
};
- pcie@3400000 {
+ pcie1: pcie@3400000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03400000 0x0 0x80000 /* PAB registers */
0x00 0x03480000 0x0 0x40000 /* LUT registers */
0x00 0x034c0000 0x0 0x40000 /* PF control registers */
- 0x80 0x00000000 0x0 0x1000>; /* configuration space */
+ 0x80 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
+ ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
- pcie@3500000 {
+ pcie2: pcie@3500000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03500000 0x0 0x80000 /* PAB registers */
0x00 0x03580000 0x0 0x40000 /* LUT registers */
0x00 0x035c0000 0x0 0x40000 /* PF control registers */
- 0x88 0x00000000 0x0 0x1000>; /* configuration space */
+ 0x88 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
num-lanes = <2>;
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>;
+ ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
- pcie@3600000 {
+ pcie3: pcie@3600000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03600000 0x0 0x80000 /* PAB registers */
0x00 0x03680000 0x0 0x40000 /* LUT registers */
0x00 0x036c0000 0x0 0x40000 /* PF control registers */
- 0x90 0x00000000 0x0 0x1000>; /* configuration space */
+ 0x90 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>;
+ ranges = <0x81000000 0x0 0x00000000 0x90 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x90 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
- pcie@3700000 {
+ pcie4: pcie@3700000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03700000 0x0 0x80000 /* PAB registers */
0x00 0x03780000 0x0 0x40000 /* LUT registers */
0x00 0x037c0000 0x0 0x40000 /* PF control registers */
- 0x98 0x00000000 0x0 0x1000>; /* configuration space */
+ 0x98 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>;
+ ranges = <0x81000000 0x0 0x00000000 0x98 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x98 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
- pcie@3800000 {
+ pcie5: pcie@3800000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03800000 0x0 0x80000 /* PAB registers */
0x00 0x03880000 0x0 0x40000 /* LUT registers */
0x00 0x038c0000 0x0 0x40000 /* PF control registers */
- 0xa0 0x00000000 0x0 0x1000>; /* configuration space */
+ 0xa0 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>;
+ ranges = <0x81000000 0x0 0x00000000 0xa0 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0xa0 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
};
- pcie@3900000 {
+ pcie6: pcie@3900000 {
compatible = "fsl,lx2160a-pcie";
reg = <0x00 0x03900000 0x0 0x80000 /* PAB registers */
0x00 0x03980000 0x0 0x40000 /* LUT registers */
0x00 0x039c0000 0x0 0x40000 /* PF control registers */
- 0xa8 0x00000000 0x0 0x1000>; /* configuration space */
+ 0xa8 0x00000000 0x0 0x2000>; /* configuration space */
reg-names = "ccsr", "lut", "pf_ctrl", "config";
#address-cells = <3>;
#size-cells = <2>;
device_type = "pci";
bus-range = <0x0 0xff>;
- ranges = <0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>;
+ ranges = <0x81000000 0x0 0x00000000 0xa8 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0xa8 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ fsl_mc: fsl-mc@80c000000 {
+ compatible = "fsl,qoriq-mc", "simple-mfd";
+ reg = <0x00000008 0x0c000000 0 0x40>,
+ <0x00000000 0x08340000 0 0x40000>;
+ #address-cells = <3>;
+ #size-cells = <1>;
+
+ /*
+ * Region type 0x0 - MC portals
+ * Region type 0x1 - QBMAN portals
+ */
+ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000
+ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>;
+
+ dpmacs {
+ compatible = "simple-mfd";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ dpmac1: dpmac@1 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x1>;
+ status = "disabled";
+ };
+
+ dpmac2: dpmac@2 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x2>;
+ status = "disabled";
+ };
+
+ dpmac3: dpmac@3 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x3>;
+ status = "disabled";
+ };
+
+ dpmac4: dpmac@4 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x4>;
+ status = "disabled";
+ };
+
+ dpmac5: dpmac@5 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x5>;
+ status = "disabled";
+ };
+
+ dpmac6: dpmac@6 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x6>;
+ status = "disabled";
+ };
+
+ dpmac7: dpmac@7 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x7>;
+ status = "disabled";
+ };
+
+ dpmac8: dpmac@8 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x8>;
+ status = "disabled";
+ };
+
+ dpmac9: dpmac@9 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x9>;
+ status = "disabled";
+ };
+
+ dpmac10: dpmac@a {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xa>;
+ status = "disabled";
+ };
+
+ dpmac11: dpmac@b {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xb>;
+ status = "disabled";
+ };
+
+ dpmac12: dpmac@c {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xc>;
+ status = "disabled";
+ };
+
+ dpmac13: dpmac@d {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xd>;
+ status = "disabled";
+ };
+
+ dpmac14: dpmac@e {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xe>;
+ status = "disabled";
+ };
+
+ dpmac15: dpmac@f {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0xf>;
+ status = "disabled";
+ };
+
+ dpmac16: dpmac@10 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x10>;
+ status = "disabled";
+ };
+
+ dpmac17: dpmac@11 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x11>;
+ status = "disabled";
+ };
+
+ dpmac18: dpmac@12 {
+ compatible = "fsl,qoriq-mc-dpmac";
+ reg = <0x12>;
+ status = "disabled";
+ };
+ };
+ };
+
+ /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */
+ emdio1: mdio@8b96000 {
+ compatible = "fsl,ls-mdio";
+ reg = <0x0 0x8b96000 0x0 0x1000>;
+ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */
+ emdio2: mdio@8b97000 {
+ compatible = "fsl,ls-mdio";
+ reg = <0x0 0x8b97000 0x0 0x1000>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ firmware {
+ optee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
};
};
projects / platform / kernel / u-boot.git / blobdiff