Merge tag 'u-boot-atmel-fixes-2021.01-b' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / arch / arm / dts / fsl-ls2080a.dtsi

diff --git a/arch/arm/dts/fsl-ls2080a.dtsi b/arch/arm/dts/fsl-ls2080a.dtsi
index fb5777e..f0f4a82 100644 (file)
--- a/arch/arm/dts/fsl-ls2080a.dtsi
+++ b/arch/arm/dts/fsl-ls2080a.dtsi
@@ -1,7 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+ OR X11
 /*
- * Freescale ls2080a SOC common device tree source
+ * NXP ls2080a SOC common device tree source
  *
+ * Copyright 2020 NXP
  * Copyright 2013-2015 Freescale Semiconductor, Inc.
  */
 
@@ -26,6 +27,12 @@
                interrupts = <1 9 0x4>;
        };
 
+       gic_lpi_base: syscon@0x80000000 {
+               compatible = "gic-lpi-base";
+               reg = <0x0 0x80000000 0x0 0x100000>;
+               max-gic-redistributors = <8>;
+       };
+
        timer {
                compatible = "arm,armv8-timer";
                interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
@@ -96,13 +103,13 @@
        };
 
        qspi: quadspi@1550000 {
-               compatible = "fsl,vf610-qspi";
+               compatible = "fsl,ls2080a-qspi";
                #address-cells = <1>;
                #size-cells = <0>;
                reg = <0x0 0x20c0000 0x0 0x10000>,
                        <0x0 0x20000000 0x0 0x10000000>;
                reg-names = "QuadSPI", "QuadSPI-memory";
-               num-cs = <4>;
+               status = "disabled";
        };
 
        esdhc: esdhc@0 {
@@ -127,7 +134,7 @@
                dr_mode = "host";
        };
 
-       pcie@3400000 {
+       pcie1: pcie@3400000 {
                compatible = "fsl,ls-pcie", "snps,dw-pcie";
                reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
                       0x00 0x03480000 0x0 0x80000   /* lut registers */
@@ -142,7 +149,7 @@
                          0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
        };
 
-       pcie@3500000 {
+       pcie2: pcie@3500000 {
                compatible = "fsl,ls-pcie", "snps,dw-pcie";
                reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
                       0x00 0x03580000 0x0 0x80000   /* lut registers */
@@ -157,7 +164,7 @@
                          0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
        };
 
-       pcie@3600000 {
+       pcie3: pcie@3600000 {
                compatible = "fsl,ls-pcie", "snps,dw-pcie";
                reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
                       0x00 0x03680000 0x0 0x80000   /* lut registers */
@@ -172,7 +179,7 @@
                          0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
        };
 
-       pcie@3700000 {
+       pcie4: pcie@3700000 {
                compatible = "fsl,ls-pcie", "snps,dw-pcie";
                reg = <0x00 0x03700000 0x0 0x80000   /* dbi registers */
                       0x00 0x03780000 0x0 0x80000   /* lut registers */