+// SPDX-License-Identifier: GPL-2.0+ OR X11
/*
* NXP ls1088a SOC common device tree source
*
* Copyright 2017 NXP
- *
- * SPDX-License-Identifier: GPL-2.0+
*/
/ {
reg-names = "QuadSPI", "QuadSPI-memory";
num-cs = <4>;
};
+
+ esdhc: esdhc@2140000 {
+ compatible = "fsl,esdhc";
+ reg = <0x0 0x2140000 0x0 0x10000>;
+ interrupts = <0 28 0x4>; /* Level high type */
+ little-endian;
+ bus-width = <4>;
+ };
+
+ ifc: ifc@1530000 {
+ compatible = "fsl,ifc", "simple-bus";
+ reg = <0x0 0x2240000 0x0 0x20000>;
+ interrupts = <0 21 0x4>; /* Level high type */
+ };
+
+ usb0: usb3@3100000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3100000 0x0 0x10000>;
+ interrupts = <0 80 0x4>; /* Level high type */
+ dr_mode = "host";
+ };
+
+ usb1: usb3@3110000 {
+ compatible = "fsl,layerscape-dwc3";
+ reg = <0x0 0x3110000 0x0 0x10000>;
+ interrupts = <0 81 0x4>; /* Level high type */
+ dr_mode = "host";
+ };
+
+ pcie@3400000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03400000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03480000 0x0 0x80000 /* lut registers */
+ 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */
+ 0x20 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x20 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie@3500000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03500000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03580000 0x0 0x80000 /* lut registers */
+ 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */
+ 0x28 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <4>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x28 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ pcie@3600000 {
+ compatible = "fsl,ls-pcie", "snps,dw-pcie";
+ reg = <0x00 0x03600000 0x0 0x80000 /* dbi registers */
+ 0x00 0x03680000 0x0 0x80000 /* lut registers */
+ 0x00 0x036c0000 0x0 0x40000 /* pf controls registers */
+ 0x30 0x00000000 0x0 0x20000>; /* configuration space */
+ reg-names = "dbi", "lut", "ctrl", "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ num-lanes = <8>;
+ bus-range = <0x0 0xff>;
+ ranges = <0x81000000 0x0 0x00000000 0x30 0x00020000 0x0 0x00010000 /* downstream I/O */
+ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+ };
+
+ sata: sata@3200000 {
+ compatible = "fsl,ls1088a-ahci";
+ reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */
+ 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/
+ reg-names = "sata-base", "ecc-addr";
+ interrupts = <0 133 4>;
+ status = "disabled";
+ };
+
};