ARM: dts: am43xx-clocks: add spread spectrum support
[platform/kernel/u-boot.git] / arch / arm / dts / am43xx-clocks.dtsi
index d0c0dfa..b1127b5 100644 (file)
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-core-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x2d20>, <0x2d24>, <0x2d2c>;
+               reg = <0x2d20>, <0x2d24>, <0x2d2c>, <0x2d48>, <0x2d4c>;
        };
 
        dpll_core_x2_ck: dpll_core_x2_ck {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x2d60>, <0x2d64>, <0x2d6c>;
+               reg = <0x2d60>, <0x2d64>, <0x2d6c>, <0x2d88>, <0x2d8c>;
        };
 
        dpll_mpu_m2_ck: dpll_mpu_m2_ck {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x2da0>, <0x2da4>, <0x2dac>;
+               reg = <0x2da0>, <0x2da4>, <0x2dac>, <0x2dc8>, <0x2dcc>;
        };
 
        dpll_ddr_m2_ck: dpll_ddr_m2_ck {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x2e20>, <0x2e24>, <0x2e2c>;
+               reg = <0x2e20>, <0x2e24>, <0x2e2c>, <0x2e48>, <0x2e4c>;
        };
 
        dpll_disp_m2_ck: dpll_disp_m2_ck {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-j-type-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x2de0>, <0x2de4>, <0x2dec>;
+               reg = <0x2de0>, <0x2de4>, <0x2dec>, <0x2e08>, <0x2e0c>;
        };
 
        dpll_per_m2_ck: dpll_per_m2_ck {
                #clock-cells = <0>;
                compatible = "ti,am3-dpll-clock";
                clocks = <&sys_clkin_ck>, <&sys_clkin_ck>;
-               reg = <0x2e60>, <0x2e64>, <0x2e6c>;
+               reg = <0x2e60>, <0x2e64>, <0x2e6c>, <0x2e88>, <0x2e8c>;
        };
 
        dpll_extdev_m2_ck: dpll_extdev_m2_ck {