+// SPDX-License-Identifier: GPL-2.0+
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Alex Zuepke <azu@sysgo.de>
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
*/
+#include <common.h>
+#include <cpu_func.h>
+#include <irq_func.h>
+#include <asm/arch/pxa-regs.h>
+#include <asm/cache.h>
#include <asm/io.h>
#include <asm/system.h>
#include <command.h>
-#include <common.h>
-#include <asm/arch/pxa-regs.h>
/* Flush I/D-cache */
static void cache_flush(void)
return 0;
}
-void pxa_wait_ticks(int ticks)
-{
- writel(0, OSCR);
- while (readl(OSCR) < ticks)
- asm volatile("" : : : "memory");
-}
-
inline void writelrb(uint32_t val, uint32_t addr)
{
writel(val, addr);
writelrb(CONFIG_SYS_MDCNFG_VAL &
~(MDCNFG_DE0 | MDCNFG_DE1 | MDCNFG_DE2 | MDCNFG_DE3), MDCNFG);
+
/* Wait for the clock to the SDRAMs to stabilize, 100..200 usec. */
- pxa_wait_ticks(0x300);
+ writel(0, OSCR);
+ while (readl(OSCR) < 0x300)
+ asm volatile("" : : : "memory");
/*
* 8) Trigger a number (usually 8) refresh cycles by attempting
{
writel(CONFIG_SYS_CKEN, CKEN);
writel(CONFIG_SYS_CCCR, CCCR);
- asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(2));
+ asm volatile("mcr p14, 0, %0, c6, c0, 0" : : "r"(0x0b));
/* enable the 32Khz oscillator for RTC and PowerManager */
writel(OSCC_OON, OSCC);
tmp = readl(OSCR);
tmp += 0x1000;
writel(tmp, OSMR3);
+ writel(MDREFR_SLFRSH, MDREFR);
for (;;)
;
}
+
+void enable_caches(void)
+{
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
+ icache_enable();
+#endif
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
+ dcache_enable();
+#endif
+}