Merge tag 'ti-v2021.01-rc1' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti

[platform/kernel/u-boot.git] / arch / arm / cpu / armv8 / start.S

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 12a78ee..6624491 100644 (file)
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -18,7 +18,7 @@
 
 .globl _start
 _start:
-#if defined(LINUX_KERNEL_IMAGE_HEADER)
+#if defined(CONFIG_LINUX_KERNEL_IMAGE_HEADER)
 #include <asm/boot0-linux-kernel-header.h>
 #elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
 /*
@@ -59,6 +59,23 @@ reset:
 save_boot_params_ret:
 
 #if CONFIG_POSITION_INDEPENDENT
+       /* Verify that we're 4K aligned.  */
+       adr     x0, _start
+       ands    x0, x0, #0xfff
+       b.eq    1f
+0:
+       /*
+        * FATAL, can't continue.
+        * U-Boot needs to be loaded at a 4K aligned address.
+        *
+        * We use ADRP and ADD to load some symbol addresses during startup.
+        * The ADD uses an absolute (non pc-relative) lo12 relocation
+        * thus requiring 4K alignment.
+        */
+       wfi
+       b       0b
+1:
+
        /*
         * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
         * executed at a different address than it was linked at.
@@ -66,9 +83,12 @@ save_boot_params_ret:
 pie_fixup:
        adr     x0, _start              /* x0 <- Runtime value of _start */
        ldr     x1, _TEXT_BASE          /* x1 <- Linked value of _start */
-       sub     x9, x0, x1              /* x9 <- Run-vs-link offset */
-       adr     x2, __rel_dyn_start     /* x2 <- Runtime &__rel_dyn_start */
-       adr     x3, __rel_dyn_end       /* x3 <- Runtime &__rel_dyn_end */
+       subs    x9, x0, x1              /* x9 <- Run-vs-link offset */
+       beq     pie_fixup_done
+       adrp    x2, __rel_dyn_start     /* x2 <- Runtime &__rel_dyn_start */
+       add     x2, x2, #:lo12:__rel_dyn_start
+       adrp    x3, __rel_dyn_end       /* x3 <- Runtime &__rel_dyn_end */
+       add     x3, x3, #:lo12:__rel_dyn_end
 pie_fix_loop:
        ldp     x0, x1, [x2], #16       /* (x0, x1) <- (Link location, fixup) */
        ldr     x4, [x2], #8            /* x4 <- addend */
@@ -88,7 +108,7 @@ pie_fixup_done:
        bl reset_sctrl
 #endif
 
-#if defined(CONFIG_ARMV8__SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
 .macro set_vbar, regname, reg
        msr     \regname, \reg
 .endm
@@ -120,6 +140,7 @@ pie_fixup_done:
        mov     x0, #3 << 20
        msr     cpacr_el1, x0                   /* Enable FP/SIMD */
 0:
+       isb
 
        /*
         * Enable SMPEN bit for coherency.
@@ -132,6 +153,7 @@ pie_fixup_done:
        mrs     x0, S3_1_c15_c2_1               /* cpuectlr_el1 */
        orr     x0, x0, #0x40
        msr     S3_1_c15_c2_1, x0
+       isb
 1:
 #endif
 
@@ -233,6 +255,7 @@ apply_a53_core_errata:
        /* Enable data cache clean as data cache clean/invalidate */
        orr     x0, x0, #1 << 44
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
        b 0b
 
@@ -247,6 +270,7 @@ apply_a57_core_errata:
        /* Disable write streaming no-allocate threshold */
        orr     x0, x0, #3 << 27
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_826974
@@ -254,6 +278,7 @@ apply_a57_core_errata:
        /* Disable speculative load execution ahead of a DMB */
        orr     x0, x0, #1 << 59
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_833471
@@ -263,6 +288,7 @@ apply_a57_core_errata:
            could impact performance. */
        orr     x0, x0, #1 << 38
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_829520
@@ -273,6 +299,7 @@ apply_a57_core_errata:
            could impact performance. */
        orr     x0, x0, #1 << 4
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_833069
@@ -280,6 +307,7 @@ apply_a57_core_errata:
        /* Disable Enable Invalidates of BTB bit */
        and     x0, x0, #0xE
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
        b 0b
 ENDPROC(apply_core_errata)
@@ -354,7 +382,7 @@ ENDPROC(smp_kick_all_cpus)
 /*-----------------------------------------------------------------------*/
 
 ENTRY(c_runtime_cpu_setup)
-#if defined(CONFIG_ARMV8__SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
+#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
        /* Relocate vBAR */
        adr     x0, vectors
        switch_el x1, 3f, 2f, 1f