.globl _start
_start:
- b reset
-
#ifdef CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK
/*
* Various SoCs need something special and SoC-specific up front in
* use it here.
*/
#include <asm/arch/boot0.h>
-ARM_SOC_BOOT0_HOOK
+#else
+ b reset
#endif
.align 3
.quad __bss_end - _start
reset:
+ /* Allow the board to save important registers */
+ b save_boot_params
+.globl save_boot_params_ret
+save_boot_params_ret:
+
#ifdef CONFIG_SYS_RESET_SCTRL
bl reset_sctrl
#endif
msr cpacr_el1, x0 /* Enable FP/SIMD */
0:
+ /*
+ * Enable SMPEN bit for coherency.
+ * This register is not architectural but at the moment
+ * this bit should be set for A53/A57/A72.
+ */
+#ifdef CONFIG_ARMV8_SET_SMPEN
+ mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */
+ orr x0, x0, #0x40
+ msr S3_1_c15_c2_1, x0
+#endif
+
/* Apply ARM core specific erratas */
bl apply_core_errata
/* Processor specific initialization */
bl lowlevel_init
-#if CONFIG_IS_ENABLED(ARMV8_SPIN_TABLE)
+#if defined(CONFIG_ARMV8_SPIN_TABLE) && !defined(CONFIG_SPL_BUILD)
branch_if_master x0, x1, master_cpu
b spin_table_secondary_jump
/* never return */
/*
* All slaves will enter EL2 and optionally EL1.
*/
+ adr x4, lowlevel_in_el2
+ ldr x5, =ES_TO_AARCH64
bl armv8_switch_to_el2
+
+lowlevel_in_el2:
#ifdef CONFIG_ARMV8_SWITCH_TO_EL1
+ adr x4, lowlevel_in_el1
+ ldr x5, =ES_TO_AARCH64
bl armv8_switch_to_el1
+
+lowlevel_in_el1:
#endif
#endif /* CONFIG_ARMV8_MULTIENTRY */
ret
ENDPROC(c_runtime_cpu_setup)
+
+WEAK(save_boot_params)
+ b save_boot_params_ret /* back to my caller */
+ENDPROC(save_boot_params)