arm64: issue ISB after updating system registers

[platform/kernel/u-boot.git] / arch / arm / cpu / armv8 / start.S

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index ecee9e3..002698b 100644 (file)
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -18,7 +18,7 @@
 
 .globl _start
 _start:
-#if defined(LINUX_KERNEL_IMAGE_HEADER)
+#if defined(CONFIG_LINUX_KERNEL_IMAGE_HEADER)
 #include <asm/boot0-linux-kernel-header.h>
 #elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
 /*
@@ -26,11 +26,7 @@ _start:
  * order to boot, allow them to set that in their boot0.h file and then
  * use it here.
  */
-#ifdef CONFIG_ARCH_ROCKCHIP
-#include <asm/arch-rockchip/boot0.h>
-#else
 #include <asm/arch/boot0.h>
-#endif
 #else
        b       reset
 #endif
@@ -124,6 +120,7 @@ pie_fixup_done:
        mov     x0, #3 << 20
        msr     cpacr_el1, x0                   /* Enable FP/SIMD */
 0:
+       isb
 
        /*
         * Enable SMPEN bit for coherency.
@@ -136,6 +133,7 @@ pie_fixup_done:
        mrs     x0, S3_1_c15_c2_1               /* cpuectlr_el1 */
        orr     x0, x0, #0x40
        msr     S3_1_c15_c2_1, x0
+       isb
 1:
 #endif
 
@@ -237,6 +235,7 @@ apply_a53_core_errata:
        /* Enable data cache clean as data cache clean/invalidate */
        orr     x0, x0, #1 << 44
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
        b 0b
 
@@ -251,6 +250,7 @@ apply_a57_core_errata:
        /* Disable write streaming no-allocate threshold */
        orr     x0, x0, #3 << 27
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_826974
@@ -258,6 +258,7 @@ apply_a57_core_errata:
        /* Disable speculative load execution ahead of a DMB */
        orr     x0, x0, #1 << 59
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_833471
@@ -267,6 +268,7 @@ apply_a57_core_errata:
            could impact performance. */
        orr     x0, x0, #1 << 38
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_829520
@@ -277,6 +279,7 @@ apply_a57_core_errata:
            could impact performance. */
        orr     x0, x0, #1 << 4
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_833069
@@ -284,6 +287,7 @@ apply_a57_core_errata:
        /* Disable Enable Invalidates of BTB bit */
        and     x0, x0, #0xE
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
        b 0b
 ENDPROC(apply_core_errata)