arm64: issue ISB after updating system registers

[platform/kernel/u-boot.git] / arch / arm / cpu / armv8 / start.S

diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S
index 7a98a1c..002698b 100644 (file)
--- a/arch/arm/cpu/armv8/start.S
+++ b/arch/arm/cpu/armv8/start.S
@@ -1,8 +1,7 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2013
  * David Feng <fenghua@phytium.com.cn>
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <asm-offsets.h>
@@ -19,7 +18,7 @@
 
 .globl _start
 _start:
-#if defined(LINUX_KERNEL_IMAGE_HEADER)
+#if defined(CONFIG_LINUX_KERNEL_IMAGE_HEADER)
 #include <asm/boot0-linux-kernel-header.h>
 #elif defined(CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK)
 /*
@@ -88,13 +87,22 @@ pie_fixup_done:
 #ifdef CONFIG_SYS_RESET_SCTRL
        bl reset_sctrl
 #endif
+
+#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
+.macro set_vbar, regname, reg
+       msr     \regname, \reg
+.endm
+       adr     x0, vectors
+#else
+.macro set_vbar, regname, reg
+.endm
+#endif
        /*
         * Could be EL3/EL2/EL1, Initial State:
         * Little Endian, MMU Disabled, i/dCache Disabled
         */
-       adr     x0, vectors
        switch_el x1, 3f, 2f, 1f
-3:     msr     vbar_el3, x0
+3:     set_vbar vbar_el3, x0
        mrs     x0, scr_el3
        orr     x0, x0, #0xf                    /* SCR_EL3.NS|IRQ|FIQ|EA */
        msr     scr_el3, x0
@@ -104,14 +112,15 @@ pie_fixup_done:
        msr     cntfrq_el0, x0                  /* Initialize CNTFRQ */
 #endif
        b       0f
-2:     msr     vbar_el2, x0
+2:     set_vbar        vbar_el2, x0
        mov     x0, #0x33ff
        msr     cptr_el2, x0                    /* Enable FP/SIMD */
        b       0f
-1:     msr     vbar_el1, x0
+1:     set_vbar        vbar_el1, x0
        mov     x0, #3 << 20
        msr     cpacr_el1, x0                   /* Enable FP/SIMD */
 0:
+       isb
 
        /*
         * Enable SMPEN bit for coherency.
@@ -124,6 +133,7 @@ pie_fixup_done:
        mrs     x0, S3_1_c15_c2_1               /* cpuectlr_el1 */
        orr     x0, x0, #0x40
        msr     S3_1_c15_c2_1, x0
+       isb
 1:
 #endif
 
@@ -225,6 +235,7 @@ apply_a53_core_errata:
        /* Enable data cache clean as data cache clean/invalidate */
        orr     x0, x0, #1 << 44
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
        b 0b
 
@@ -239,6 +250,7 @@ apply_a57_core_errata:
        /* Disable write streaming no-allocate threshold */
        orr     x0, x0, #3 << 27
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_826974
@@ -246,6 +258,7 @@ apply_a57_core_errata:
        /* Disable speculative load execution ahead of a DMB */
        orr     x0, x0, #1 << 59
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_833471
@@ -255,6 +268,7 @@ apply_a57_core_errata:
            could impact performance. */
        orr     x0, x0, #1 << 38
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_829520
@@ -265,6 +279,7 @@ apply_a57_core_errata:
            could impact performance. */
        orr     x0, x0, #1 << 4
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
 
 #ifdef CONFIG_ARM_ERRATA_833069
@@ -272,6 +287,7 @@ apply_a57_core_errata:
        /* Disable Enable Invalidates of BTB bit */
        and     x0, x0, #0xE
        msr     S3_1_c15_c2_0, x0       /* cpuactlr_el1 */
+       isb
 #endif
        b 0b
 ENDPROC(apply_core_errata)
@@ -346,6 +362,7 @@ ENDPROC(smp_kick_all_cpus)
 /*-----------------------------------------------------------------------*/
 
 ENTRY(c_runtime_cpu_setup)
+#if defined(CONFIG_ARMV8_SPL_EXCEPTION_VECTORS) || !defined(CONFIG_SPL_BUILD)
        /* Relocate vBAR */
        adr     x0, vectors
        switch_el x1, 3f, 2f, 1f
@@ -355,6 +372,7 @@ ENTRY(c_runtime_cpu_setup)
        b       0f
 1:     msr     vbar_el1, x0
 0:
+#endif
 
        ret
 ENDPROC(c_runtime_cpu_setup)