global: Migrate CONFIG_SYS_FSL* symbols to the CFG_SYS namespace

[platform/kernel/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / lowlevel.S

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
index d880373..4358c6e 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
+++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2014-2015 Freescale Semiconductor
- * Copyright 2019 NXP
+ * Copyright 2019-2022 NXP
  *
  * Extracted from armv8/start.S
  */
@@ -74,15 +74,6 @@ ENDPROC(smp_kick_all_cpus)
 ENTRY(lowlevel_init)
        mov     x29, lr                 /* Save LR */
 
-       /* unmask SError and abort */
-       msr daifclr, #4
-
-       /* Set HCR_EL2[AMO] so SError @EL2 is taken */
-       mrs     x0, hcr_el2
-       orr     x0, x0, #0x20                   /* AMO */
-       msr     hcr_el2, x0
-       isb
-
        switch_el x1, 1f, 100f, 100f    /* skip if not in EL3 */
 1:
 
@@ -209,7 +200,7 @@ ENTRY(lowlevel_init)
 #endif
 
 100:
-       branch_if_master x0, x1, 2f
+       branch_if_master x0, 2f
 
 #if defined(CONFIG_MP) && defined(CONFIG_ARMV8_MULTIENTRY)
        /*
@@ -250,7 +241,7 @@ ENTRY(lowlevel_init)
         * b. We use only Region0 whose NSAID write/read is EN
         *
         * NOTE: As per the CCSR map doc, TZASC 3 and TZASC 4 are just
-        *       placeholders.
+        *       placeholders.
         */
 
 .macro tzasc_prog, xreg
@@ -259,7 +250,7 @@ ENTRY(lowlevel_init)
        mov     x16, #0x10000
        mul     x14, \xreg, x16
        add     x14, x14,x12
-       mov     x1, #0x8
+       mov     x1, #0x8
        add     x1, x1, x14
 
        ldr     w0, [x1]                /* Filter 0 Gate Keeper Register */
@@ -334,8 +325,8 @@ ENDPROC(fsl_ocram_init)
 
 ENTRY(fsl_clear_ocram)
 /* Clear OCRAM */
-       ldr     x0, =CONFIG_SYS_FSL_OCRAM_BASE
-       ldr     x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE)
+       ldr     x0, =CFG_SYS_FSL_OCRAM_BASE
+       ldr     x1, =(CFG_SYS_FSL_OCRAM_BASE + CFG_SYS_FSL_OCRAM_SIZE)
        mov     x2, #0
 clear_loop:
        str     x2, [x0]
@@ -353,7 +344,7 @@ ENTRY(fsl_ocram_clear_ecc_err)
        ldr     x0, =DCSR_DCFG_MBEESR2
        str     w1, [x0]
        ret
-ENDPROC(fsl_ocram_init)
+ENDPROC(fsl_ocram_clear_ecc_err)
 #endif
 
 #ifdef CONFIG_FSL_LSCH3