Merge tag 'u-boot-atmel-fixes-2021.01-b' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / fsl_lsch3_speed.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
index ede9674..bf153c7 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c
@@ -1,12 +1,14 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014-2015, Freescale Semiconductor, Inc.
- * Copyright 2019 NXP Semiconductors
+ * Copyright 2019-2020 NXP
  *
  * Derived from arch/power/cpu/mpc85xx/speed.c
  */
 
 #include <common.h>
+#include <clock_legacy.h>
+#include <cpu_func.h>
 #include <linux/compiler.h>
 #include <fsl_ifc.h>
 #include <asm/processor.h>
@@ -159,14 +161,14 @@ void get_sys_info(struct sys_info *sys_info)
                break;
        }
 #endif
-#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A)
-       sys_info->freq_cga_m2 = sys_info->freq_systembus;
-#endif
 }
 
 int get_clocks(void)
 {
        struct sys_info sys_info;
+#ifdef CONFIG_FSL_ESDHC
+       u32 clock = 0;
+#endif
        get_sys_info(&sys_info);
        gd->cpu_clk = sys_info.freq_processor[0];
        gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
@@ -174,18 +176,16 @@ int get_clocks(void)
 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
        gd->arch.mem2_clk = sys_info.freq_ddrbus2;
 #endif
-#if defined(CONFIG_FSL_ESDHC)
-#if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK)
-#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A)
-       gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2;
-#endif
-#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
-       gd->arch.sdhc_clk = sys_info.freq_cga_m2;
+
+#ifdef CONFIG_FSL_ESDHC
+#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
+       clock = sys_info.freq_cga_m2;
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2162A)
+       clock = sys_info.freq_systembus;
 #endif
-#else
+       gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
        gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
 #endif
-#endif /* defined(CONFIG_FSL_ESDHC) */
 
        if (gd->cpu_clk != 0)
                return 0;