+// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2014-2015, Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright 2019-2020 NXP
*
* Derived from arch/power/cpu/mpc85xx/speed.c
*/
#include <common.h>
+#include <clock_legacy.h>
+#include <cpu_func.h>
#include <linux/compiler.h>
#include <fsl_ifc.h>
#include <asm/processor.h>
};
uint i, cluster;
+#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
+ uint rcw_tmp;
+#endif
uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS];
uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS];
unsigned long sysclk = CONFIG_SYS_CLK_FREQ;
sys_info->freq_localbus = sys_info->freq_systembus /
CONFIG_SYS_FSL_IFC_CLK_DIV;
#endif
-}
+#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
+#define HWA_CGA_M2_CLK_SEL 0x00380000
+#define HWA_CGA_M2_CLK_SHIFT 19
+ rcw_tmp = in_le32(&gur->rcwsr[5]);
+ switch ((rcw_tmp & HWA_CGA_M2_CLK_SEL) >> HWA_CGA_M2_CLK_SHIFT) {
+ case 1:
+ sys_info->freq_cga_m2 = freq_c_pll[1];
+ break;
+ case 2:
+ sys_info->freq_cga_m2 = freq_c_pll[1] / 2;
+ break;
+ case 3:
+ sys_info->freq_cga_m2 = freq_c_pll[1] / 3;
+ break;
+ case 4:
+ sys_info->freq_cga_m2 = freq_c_pll[1] / 4;
+ break;
+ case 6:
+ sys_info->freq_cga_m2 = freq_c_pll[0] / 2;
+ break;
+ case 7:
+ sys_info->freq_cga_m2 = freq_c_pll[0] / 3;
+ break;
+ default:
+ printf("Error: Unknown peripheral clock select!\n");
+ break;
+ }
+#endif
+}
int get_clocks(void)
{
struct sys_info sys_info;
+#ifdef CONFIG_FSL_ESDHC
+ u32 clock = 0;
+#endif
get_sys_info(&sys_info);
gd->cpu_clk = sys_info.freq_processor[0];
gd->bus_clk = sys_info.freq_systembus / CONFIG_SYS_FSL_PCLK_DIV;
#ifdef CONFIG_SYS_FSL_HAS_DP_DDR
gd->arch.mem2_clk = sys_info.freq_ddrbus2;
#endif
-#if defined(CONFIG_FSL_ESDHC)
+
+#ifdef CONFIG_FSL_ESDHC
+#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A)
+ clock = sys_info.freq_cga_m2;
+#elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2162A)
+ clock = sys_info.freq_systembus;
+#endif
+ gd->arch.sdhc_per_clk = clock / CONFIG_SYS_FSL_SDHC_CLK_DIV;
gd->arch.sdhc_clk = gd->bus_clk / CONFIG_SYS_FSL_SDHC_CLK_DIV;
-#endif /* defined(CONFIG_FSL_ESDHC) */
+#endif
if (gd->cpu_clk != 0)
return 0;