Merge branch 'master' of git://git.denx.de/u-boot-sunxi

[platform/kernel/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / fsl_lsch3_serdes.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
index 9ee0dd2..1a747a9 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c
@@ -1,7 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
+ * Copyright 2016-2018 NXP
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
@@ -17,11 +17,23 @@ static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT];
 #ifdef CONFIG_SYS_FSL_SRDS_2
 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT];
 #endif
+#ifdef CONFIG_SYS_NXP_SRDS_3
+static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT];
+#endif
 
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#ifdef CONFIG_ARCH_LX2160A
+int xfi_dpmac[XFI14 + 1];
+int sgmii_dpmac[SGMII18 + 1];
+int a25gaui_dpmac[_25GE10 + 1];
+int xlaui_dpmac[_40GE2 + 1];
+int caui2_dpmac[_50GE2 + 1];
+int caui4_dpmac[_100GE2 + 1];
+#else
 int xfi_dpmac[XFI8 + 1];
 int sgmii_dpmac[SGMII16 + 1];
 #endif
+#endif
 
 __weak void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl)
 {
@@ -58,6 +70,12 @@ int is_serdes_configured(enum srds_prtcl device)
 
        ret |= serdes2_prtcl_map[device];
 #endif
+#ifdef CONFIG_SYS_NXP_SRDS_3
+       if (!serdes3_prtcl_map[NONE])
+               fsl_serdes_init();
+
+       ret |= serdes3_prtcl_map[device];
+#endif
 
        return !!ret;
 }
@@ -83,6 +101,13 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
                cfg >>= FSL_CHASSIS3_SRDS2_PRTCL_SHIFT;
                break;
 #endif
+#ifdef CONFIG_SYS_NXP_SRDS_3
+       case NXP_SRDS_3:
+               cfg = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
+               cfg &= FSL_CHASSIS3_SRDS3_PRTCL_MASK;
+               cfg >>= FSL_CHASSIS3_SRDS3_PRTCL_SHIFT;
+               break;
+#endif
        default:
                printf("invalid SerDes%d\n", sd);
                break;
@@ -130,6 +155,32 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
                else {
                        serdes_prtcl_map[lane_prtcl] = 1;
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
+#ifdef CONFIG_ARCH_LX2160A
+                       if (lane_prtcl >= XFI1 && lane_prtcl <= XFI14)
+                               wriop_init_dpmac(sd, xfi_dpmac[lane_prtcl],
+                                                (int)lane_prtcl);
+
+                       if (lane_prtcl >= SGMII1 && lane_prtcl <= SGMII18)
+                               wriop_init_dpmac(sd, sgmii_dpmac[lane_prtcl],
+                                                (int)lane_prtcl);
+
+                       if (lane_prtcl >= _25GE1 && lane_prtcl <= _25GE10)
+                               wriop_init_dpmac(sd, a25gaui_dpmac[lane_prtcl],
+                                                (int)lane_prtcl);
+
+                       if (lane_prtcl >= _40GE1 && lane_prtcl <= _40GE2)
+                               wriop_init_dpmac(sd, xlaui_dpmac[lane_prtcl],
+                                                (int)lane_prtcl);
+
+                       if (lane_prtcl >= _50GE1 && lane_prtcl <= _50GE2)
+                               wriop_init_dpmac(sd, caui2_dpmac[lane_prtcl],
+                                                (int)lane_prtcl);
+
+                       if (lane_prtcl >= _100GE1 && lane_prtcl <= _100GE2)
+                               wriop_init_dpmac(sd, caui4_dpmac[lane_prtcl],
+                                                (int)lane_prtcl);
+
+#else
                        switch (lane_prtcl) {
                        case QSGMII_A:
                        case QSGMII_B:
@@ -151,6 +202,7 @@ void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask,
                                break;
                        }
 #endif
+#endif
                }
        }
 
@@ -202,6 +254,12 @@ struct serdes_prctl_info srds_prctl_info[] = {
         .shift = FSL_CHASSIS3_SRDS2_PRTCL_SHIFT
        },
 #endif
+#ifdef CONFIG_SYS_NXP_SRDS_3
+       {.id = 3,
+        .mask = FSL_CHASSIS3_SRDS3_PRTCL_MASK,
+        .shift = FSL_CHASSIS3_SRDS3_PRTCL_SHIFT
+       },
+#endif
        {} /* NULL ENTRY */
 };
 
@@ -342,6 +400,11 @@ int setup_serdes_volt(u32 svdd)
                        (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000);
        u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]);
 #endif
+#ifdef CONFIG_SYS_NXP_SRDS_3
+       struct ccsr_serdes __iomem *serdes3_base =
+                       (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000);
+       u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]);
+#endif
        u32 cfg_tmp;
        int svdd_cur, svdd_tar;
        int ret = 1;
@@ -371,6 +434,9 @@ int setup_serdes_volt(u32 svdd)
 #ifdef CONFIG_SYS_FSL_SRDS_2
        do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, false);
 #endif
+#ifdef CONFIG_SYS_NXP_SRDS_3
+       do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, false);
+#endif
 
        /* Put the all enabled PLL in reset */
 #ifdef CONFIG_SYS_FSL_SRDS_1
@@ -384,6 +450,12 @@ int setup_serdes_volt(u32 svdd)
        do_pll_reset(cfg_tmp, serdes2_base);
 #endif
 
+#ifdef CONFIG_SYS_NXP_SRDS_3
+       cfg_tmp = cfg_rcwsrds3 & 0x30;
+       cfg_tmp >>= 4;
+       do_pll_reset(cfg_tmp, serdes3_base);
+#endif
+
        /* Put the Rx/Tx calibration into reset */
 #ifdef CONFIG_SYS_FSL_SRDS_1
        do_rx_tx_cal_reset(serdes1_base);
@@ -393,6 +465,10 @@ int setup_serdes_volt(u32 svdd)
        do_rx_tx_cal_reset(serdes2_base);
 #endif
 
+#ifdef CONFIG_SYS_NXP_SRDS_3
+       do_rx_tx_cal_reset(serdes3_base);
+#endif
+
        ret = set_serdes_volt(svdd);
        if (ret < 0) {
                printf("could not change SVDD\n");
@@ -409,6 +485,11 @@ int setup_serdes_volt(u32 svdd)
        cfg_tmp >>= 2;
        do_serdes_enable(cfg_tmp, serdes2_base);
 #endif
+#ifdef CONFIG_SYS_NXP_SRDS_3
+       cfg_tmp = cfg_rcwsrds3 & 0x30;
+       cfg_tmp >>= 4;
+       do_serdes_enable(cfg_tmp, serdes3_base);
+#endif
 
        /* Wait for at at least 625us, ensure the PLLs being reset are locked */
        udelay(800);
@@ -423,6 +504,13 @@ int setup_serdes_volt(u32 svdd)
        cfg_tmp >>= 2;
        do_pll_lock(cfg_tmp, serdes2_base);
 #endif
+
+#ifdef CONFIG_SYS_NXP_SRDS_3
+       cfg_tmp = cfg_rcwsrds3 & 0x30;
+       cfg_tmp >>= 4;
+       do_pll_lock(cfg_tmp, serdes3_base);
+#endif
+
        /* Take the all enabled lanes out of reset */
 #ifdef CONFIG_SYS_FSL_SRDS_1
        do_enabled_lanes_reset(1, cfg_rcwsrds1, serdes1_base, true);
@@ -431,6 +519,10 @@ int setup_serdes_volt(u32 svdd)
        do_enabled_lanes_reset(2, cfg_rcwsrds2, serdes2_base, true);
 #endif
 
+#ifdef CONFIG_SYS_NXP_SRDS_3
+       do_enabled_lanes_reset(3, cfg_rcwsrds3, serdes3_base, true);
+#endif
+
        /* For each PLL being reset, and achieved PLL lock set RST_DONE */
 #ifdef CONFIG_SYS_FSL_SRDS_1
        cfg_tmp = cfg_rcwsrds1 & 0x3;
@@ -442,6 +534,12 @@ int setup_serdes_volt(u32 svdd)
        do_pll_reset_done(cfg_tmp, serdes2_base);
 #endif
 
+#ifdef CONFIG_SYS_NXP_SRDS_3
+       cfg_tmp = cfg_rcwsrds3 & 0x30;
+       cfg_tmp >>= 4;
+       do_pll_reset_done(cfg_tmp, serdes3_base);
+#endif
+
        return ret;
 }
 
@@ -450,12 +548,32 @@ void fsl_serdes_init(void)
 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
        int i , j;
 
+#ifdef CONFIG_ARCH_LX2160A
+       for (i = XFI1, j = 1; i <= XFI14; i++, j++)
+               xfi_dpmac[i] = j;
+
+       for (i = SGMII1, j = 1; i <= SGMII18; i++, j++)
+               sgmii_dpmac[i] = j;
+
+       for (i = _25GE1, j = 1; i <= _25GE10; i++, j++)
+               a25gaui_dpmac[i] = j;
+
+       for (i = _40GE1, j = 1; i <= _40GE2; i++, j++)
+               xlaui_dpmac[i] = j;
+
+       for (i = _50GE1, j = 1; i <= _50GE2; i++, j++)
+               caui2_dpmac[i] = j;
+
+       for (i = _100GE1, j = 1; i <= _100GE2; i++, j++)
+               caui4_dpmac[i] = j;
+#else
        for (i = XFI1, j = 1; i <= XFI8; i++, j++)
                xfi_dpmac[i] = j;
 
        for (i = SGMII1, j = 1; i <= SGMII16; i++, j++)
                sgmii_dpmac[i] = j;
 #endif
+#endif
 
 #ifdef CONFIG_SYS_FSL_SRDS_1
        serdes_init(FSL_SRDS_1,
@@ -473,4 +591,12 @@ void fsl_serdes_init(void)
                    FSL_CHASSIS3_SRDS2_PRTCL_SHIFT,
                    serdes2_prtcl_map);
 #endif
+#ifdef CONFIG_SYS_NXP_SRDS_3
+       serdes_init(NXP_SRDS_3,
+                   CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000,
+                   FSL_CHASSIS3_SRDS3_REGSR,
+                   FSL_CHASSIS3_SRDS3_PRTCL_MASK,
+                   FSL_CHASSIS3_SRDS3_PRTCL_SHIFT,
+                   serdes3_prtcl_map);
+#endif
 }