Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi

[platform/kernel/u-boot.git] / arch / arm / cpu / armv8 / fsl-layerscape / fdt.c

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
index 1e7e46e..3bbad82 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c
@@ -1,9 +1,11 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014-2015 Freescale Semiconductor, Inc.
+ * Copyright 2020 NXP
  */
 
 #include <common.h>
+#include <clock_legacy.h>
 #include <efi_loader.h>
 #include <linux/libfdt.h>
 #include <fdt_support.h>
@@ -30,6 +32,14 @@
 
 int fdt_fixup_phy_connection(void *blob, int offset, phy_interface_t phyc)
 {
+       const char *conn;
+
+       /* Do NOT apply fixup for backplane modes specified in DT */
+       if (phyc == PHY_INTERFACE_MODE_XGMII) {
+               conn = fdt_getprop(blob, offset, "phy-connection-type", NULL);
+               if (is_backplane_mode(conn))
+                       return 0;
+       }
        return fdt_setprop_string(blob, offset, "phy-connection-type",
                                         phy_string_for_interface(phyc));
 }
@@ -461,6 +471,10 @@ void ft_cpu_setup(void *blob, bd_t *bd)
        do_fixup_by_path_u32(blob, "/sysclk", "clock-frequency",
                             CONFIG_SYS_CLK_FREQ, 1);
 
+#ifdef CONFIG_GIC_V3_ITS
+       ls_gic_rd_tables_init(blob);
+#endif
+
 #if defined(CONFIG_PCIE_LAYERSCAPE) || defined(CONFIG_PCIE_LAYERSCAPE_GEN4)
        ft_pci_setup(blob, bd);
 #endif