/*
+ * Copyright 2017 NXP
* Copyright 2014-2015 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
#include <asm/arch/soc.h>
#include <asm/arch/cpu.h>
#include <asm/arch/speed.h>
-#ifdef CONFIG_MP
#include <asm/arch/mp.h>
-#endif
#include <efi_loader.h>
#include <fm_eth.h>
#include <fsl-mc/fsl_mc.h>
#ifdef CONFIG_FSL_ESDHC
#include <fsl_esdhc.h>
#endif
-#ifdef CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT
#include <asm/armv8/sec_firmware.h>
-#endif
#ifdef CONFIG_SYS_FSL_DDR
#include <fsl_ddr.h>
#endif
+#include <asm/arch/clock.h>
DECLARE_GLOBAL_DATA_PTR;
static void fix_pcie_mmu_map(void)
{
-#ifdef CONFIG_LS2080A
+#ifdef CONFIG_ARCH_LS2080A
unsigned int i;
u32 svr, ver;
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
/* Fix PCIE base and size for LS2088A */
if ((ver == SVR_LS2088A) || (ver == SVR_LS2084A) ||
- (ver == SVR_LS2048A) || (ver == SVR_LS2044A)) {
+ (ver == SVR_LS2048A) || (ver == SVR_LS2044A) ||
+ (ver == SVR_LS2081A) || (ver == SVR_LS2041A)) {
for (i = 0; i < ARRAY_SIZE(final_map); i++) {
switch (final_map[i].phys) {
case CONFIG_SYS_PCIE1_PHYS_ADDR:
int arch_cpu_init(void)
{
+ /*
+ * This function is called before U-Boot relocates itself to speed up
+ * on system running. It is not necessary to run if performance is not
+ * critical. Skip if MMU is already enabled by SPL or other means.
+ */
+ if (get_sctlr() & CR_M)
+ return 0;
+
icache_enable();
__asm_invalidate_dcache_all();
__asm_invalidate_tlb_all();
{
int error = 0;
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
error = fsl_mc_ldpaa_init(bis);
#endif
#ifdef CONFIG_FMAN_ENET
return error;
}
-int arch_early_init_r(void)
+static inline int check_psci(void)
{
-#ifdef CONFIG_MP
- int rv = 1;
- u32 psci_ver = 0xffffffff;
-#endif
+ unsigned int psci_ver;
+
+ psci_ver = sec_firmware_support_psci_version();
+ if (psci_ver == PSCI_INVALID_VER)
+ return 1;
+ return 0;
+}
+
+int arch_early_init_r(void)
+{
#ifdef CONFIG_SYS_FSL_ERRATUM_A009635
u32 svr_dev_id;
/*
#if defined(CONFIG_SYS_FSL_ERRATUM_A009942) && defined(CONFIG_SYS_FSL_DDR)
erratum_a009942_check_cpo();
#endif
-#ifdef CONFIG_MP
-#if defined(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT) && \
- defined(CONFIG_SEC_FIRMWARE_ARMV8_PSCI)
- /* Check the psci version to determine if the psci is supported */
- psci_ver = sec_firmware_support_psci_version();
-#endif
- if (psci_ver == 0xffffffff) {
- rv = fsl_layerscape_wake_seconday_cores();
- if (rv)
+ if (check_psci()) {
+ debug("PSCI: PSCI does not exist.\n");
+
+ /* if PSCI does not exist, boot secondary cores here */
+ if (fsl_layerscape_wake_seconday_cores())
printf("Did not wake secondary cores\n");
}
-#endif
#ifdef CONFIG_SYS_HAS_SERDES
fsl_serdes_init();
#ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
#endif
-#ifdef CONFIG_LS2080A
+#ifdef CONFIG_ARCH_LS2080A
u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
u32 svr_dev_id;
#endif
unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
/* Update with accurate clock frequency */
- asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
+ if (current_el() == 3)
+ asm volatile("msr cntfrq_el0, %0" : : "r" (cntfrq) : "memory");
#endif
#ifdef CONFIG_FSL_LSCH3
out_le32(cltbenr, 0xf);
#endif
-#ifdef CONFIG_LS2080A
+#ifdef CONFIG_ARCH_LS2080A
/*
* In certain Layerscape SoCs, the clock for each core's
* has an enable bit in the PMU Physical Core Time Base Enable
{
phys_size_t ram_top = ram_size;
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
/* The start address of MC reserved memory needs to be aligned. */
ram_top -= mc_get_dram_block_size();
ram_top &= ~(CONFIG_SYS_MC_RSV_MEM_ALIGN - 1);
}
#endif /* CONFIG_SYS_MEM_RESERVE_SECURE */
-#ifdef CONFIG_FSL_MC_ENET
+#if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
/* Assign memory for MC */
#ifdef CONFIG_SYS_DDR_BLOCK3_BASE
if (gd->bd->bi_dram[2].size >=