select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
imply SCSI
+ imply CMD_PCI
config ARCH_LS1046A
bool
select SYS_FSL_DDR
select SYS_FSL_DDR_LE
select SYS_FSL_DDR_VER_50
+ select SYS_FSL_HAS_CCN504
select SYS_FSL_HAS_DP_DDR
select SYS_FSL_HAS_SEC
select SYS_FSL_HAS_DDR4
config FSL_LSCH2
bool
+ select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_BE
config SYS_LS_PPA_ESBC_ADDR
hex "hdr address of PPA firmware loading from"
depends on FSL_LS_PPA && CHAIN_OF_TRUST
- default 0x600c0000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
- default 0x40740000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
- default 0x40480000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
- default 0x580c40000 if SYS_LS_PPA_FW_IN_XIP && FSL_LSCH3
- default 0x700000 if SYS_LS_PPA_FW_IN_MMC
- default 0x700000 if SYS_LS_PPA_FW_IN_NAND
+ default 0x60680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1043A
+ default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1046A
+ default 0x40680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS1012A
+ default 0x20680000 if SYS_LS_PPA_FW_IN_XIP && QSPI_BOOT && ARCH_LS2080A
+ default 0x580680000 if SYS_LS_PPA_FW_IN_XIP && ARCH_LS2080A
+ default 0x680000 if SYS_LS_PPA_FW_IN_MMC
+ default 0x680000 if SYS_LS_PPA_FW_IN_NAND
help
If the PPA header firmware locate at XIP flash, such as NOR or
QSPI flash, this address is a directly memory-mapped.
But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
bus for those flashes to support the full QSPI flash size.
+config SYS_CCI400_OFFSET
+ hex "Offset for CCI400 base"
+ depends on SYS_FSL_HAS_CCI400
+ default 0x3090000 if ARCH_LS1088A
+ default 0x180000 if FSL_LSCH2
+ help
+ Offset for CCI400 base
+ CCI400 base addr = CCSRBAR + CCI400_OFFSET
+
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
default 4 if ARCH_LS1046A
default 8 if ARCH_LS2080A
+config SYS_FSL_HAS_CCI400
+ bool
+
+config SYS_FSL_HAS_CCN504
+ bool
+
config SYS_FSL_HAS_DP_DDR
bool
help
Reserved memory needs to be aligned for MC to use. Default value
is 512MB.
+
+config SPL_LDSCRIPT
+ default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A