select ARM_ERRATA_855873 if !TFABOOT
select FSL_LAYERSCAPE
select FSL_LSCH2
+ select GICV2
+ select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR_BE
select SYS_FSL_MMDC
- select SYS_FSL_ERRATUM_A010315
+ select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A008997
select SYS_FSL_ERRATUM_A009007
select SYS_I2C_MXC_I2C1 if !DM_I2C
select SYS_I2C_MXC_I2C2 if !DM_I2C
imply PANIC_HANG
+ imply TIMESTAMP
config ARCH_LS1028A
bool
select ARMV8_SET_SMPEN
+ select ESBC_HDR_LS if CHAIN_OF_TRUST
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select GICV3
select NXP_LSCH3_2
select SYS_FSL_HAS_CCI400
select SYS_FSL_SRDS_1
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
select FSL_TZASC_1
+ select FSL_TZPC_BP147
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select SYS_FSL_ERRATUM_A009663 if !TFABOOT
select SYS_FSL_ERRATUM_A009942 if !TFABOOT
select SYS_FSL_ERRATUM_A050382
+ select SYS_FSL_ERRATUM_A011334
+ select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
select RESV_RAM if GIC_V3_ITS
+ select SYS_HAS_ARMV8_SECURE_BASE
imply PANIC_HANG
config ARCH_LS1043A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
+ select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
select FSL_LAYERSCAPE
select FSL_LSCH2
+ select GICV2
+ select HAS_FSL_XHCI_USB if USB_HOST
+ select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
select SYS_FSL_DDR_VER_50
select SYS_FSL_ERRATUM_A008850 if !TFABOOT
select SYS_FSL_ERRATUM_A008997
- select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009660 if !TFABOOT
select SYS_FSL_ERRATUM_A009663 if !TFABOOT
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009942 if !TFABOOT
- select SYS_FSL_ERRATUM_A010315
+ select SYS_FSL_ERRATUM_A010315 if PCIE_LAYERSCAPE
select SYS_FSL_ERRATUM_A010539
select SYS_FSL_HAS_DDR3
select SYS_FSL_HAS_DDR4
select SYS_I2C_MXC_I2C2 if !DM_I2C
select SYS_I2C_MXC_I2C3 if !DM_I2C
select SYS_I2C_MXC_I2C4 if !DM_I2C
+ select SYS_HAS_ARMV8_SECURE_BASE
imply CMD_PCI
+ imply ID_EEPROM
config ARCH_LS1046A
bool
select ARMV8_SET_SMPEN
+ select FSL_IFC if TFABOOT || (!QSPI_BOOT && !SD_BOOT_QSPI)
select FSL_LAYERSCAPE
select FSL_LSCH2
+ select GICV2
+ select HAS_FSL_XHCI_USB if USB_HOST
+ select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
select SYS_FSL_ERRATUM_A008511 if !TFABOOT
select SYS_FSL_ERRATUM_A008850 if !TFABOOT
select SYS_FSL_ERRATUM_A008997
- select SYS_FSL_ERRATUM_A009007
select SYS_FSL_ERRATUM_A009008
select SYS_FSL_ERRATUM_A009798
select SYS_FSL_ERRATUM_A009801
select SYS_I2C_MXC_I2C2 if !DM_I2C
select SYS_I2C_MXC_I2C3 if !DM_I2C
select SYS_I2C_MXC_I2C4 if !DM_I2C
+ imply ID_EEPROM
imply SCSI
imply SCSI_AHCI
+ imply SPL_SYS_I2C_LEGACY
config ARCH_LS1088A
bool
select ARMV8_SET_SMPEN
select ARM_ERRATA_855873 if !TFABOOT
+ select ESBC_HDR_LS if CHAIN_OF_TRUST
+ select FSL_IFC
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select GICV3
+ select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
select SYS_I2C_MXC_I2C3 if !TFABOOT
select SYS_I2C_MXC_I2C4 if !TFABOOT
select RESV_RAM if GIC_V3_ITS
+ imply ID_EEPROM
imply SCSI
+ imply SPL_SYS_I2C_LEGACY
imply PANIC_HANG
config ARCH_LS2080A
select ARM_ERRATA_828024
select ARM_ERRATA_829520
select ARM_ERRATA_833471
+ select ESBC_HDR_LS if CHAIN_OF_TRUST
+ select FSL_IFC
select FSL_LAYERSCAPE
select FSL_LSCH3
+ select GICV3
+ select SKIP_LOWLEVEL_INIT
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
select SYS_FSL_DDR
select SYS_I2C_MXC_I2C4 if !TFABOOT
select RESV_RAM if GIC_V3_ITS
imply DISTRO_DEFAULTS
+ imply ID_EEPROM
imply PANIC_HANG
+ imply SPL_SYS_I2C_LEGACY
config ARCH_LX2162A
bool
select ARMV8_SET_SMPEN
+ select ESBC_HDR_LS if CHAIN_OF_TRUST
+ select FSL_DDR_BIST
+ select FSL_DDR_INTERACTIVE
+ select FSL_LAYERSCAPE
select FSL_LSCH3
+ select FSL_TZPC_BP147
+ select GICV3
select NXP_LSCH3_2
select SYS_HAS_SERDES
select SYS_FSL_SRDS_1
select SYS_FSL_DDR_VER_50
select SYS_FSL_EC1
select SYS_FSL_EC2
- select SYS_FSL_ERRATUM_A050106
+ select SYS_FSL_ERRATUM_A050204
+ select SYS_FSL_ERRATUM_A011334
+ select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
select SYS_FSL_HAS_RGMII
select SYS_FSL_HAS_SEC
select SYS_FSL_HAS_CCN508
select SYS_FSL_HAS_DDR4
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
+ select SYS_PCI_64BIT if PCI
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
imply PANIC_HANG
imply SCSI
imply SCSI_AHCI
+ imply SPL_SYS_I2C_LEGACY
config ARCH_LX2160A
bool
select ARMV8_SET_SMPEN
+ select ESBC_HDR_LS if CHAIN_OF_TRUST
+ select FSL_DDR_BIST
+ select FSL_DDR_INTERACTIVE
+ select FSL_LAYERSCAPE
select FSL_LSCH3
+ select FSL_TZPC_BP147
+ select GICV3
+ select HAS_FSL_XHCI_USB if USB_HOST
select NXP_LSCH3_2
select SYS_HAS_SERDES
select SYS_FSL_SRDS_1
select SYS_FSL_DDR_VER_50
select SYS_FSL_EC1
select SYS_FSL_EC2
- select SYS_FSL_ERRATUM_A050106
+ select SYS_FSL_ERRATUM_A050204
+ select SYS_FSL_ERRATUM_A011334
+ select SYS_FSL_ESDHC_UNRELIABLE_PULSE_DETECTION_WORKAROUND
select SYS_FSL_HAS_RGMII
select SYS_FSL_HAS_SEC
select SYS_FSL_HAS_CCN508
select SYS_FSL_HAS_DDR4
select SYS_FSL_SEC_COMPAT_5
select SYS_FSL_SEC_LE
+ select SYS_PCI_64BIT if PCI
select ARCH_EARLY_INIT_R
select BOARD_EARLY_INIT_F
select SYS_I2C_MXC
select RESV_RAM if GIC_V3_ITS
imply DISTRO_DEFAULTS
+ imply ID_EEPROM
imply PANIC_HANG
imply SCSI
imply SCSI_AHCI
+ imply SPL_SYS_I2C_LEGACY
config FSL_LSCH2
bool
+ select SKIP_LOWLEVEL_INIT
+ select SYS_FSL_CCSR_GUR_BE
+ select SYS_FSL_CCSR_SCFG_BE
+ select SYS_FSL_ESDHC_BE
+ select SYS_FSL_IFC_BE
+ select SYS_FSL_PEX_LUT_BE
select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_SEC
select SYS_FSL_SEC_COMPAT_5
config FSL_LSCH3
select ARCH_MISC_INIT
+ select SYS_FSL_CCSR_GUR_LE
+ select SYS_FSL_CCSR_SCFG_LE
+ select SYS_FSL_ESDHC_LE
+ select SYS_FSL_IFC_LE
+ select SYS_FSL_PEX_LUT_LE
bool
config NXP_LSCH3_2
bool
+config SYS_FSL_CCSR_GUR_BE
+ bool
+
+config SYS_FSL_CCSR_SCFG_BE
+ bool
+
+config SYS_FSL_PEX_LUT_BE
+ bool
+
+config SYS_FSL_CCSR_GUR_LE
+ bool
+
+config SYS_FSL_CCSR_SCFG_LE
+ bool
+
+config SYS_FSL_ESDHC_LE
+ bool
+
+config SYS_FSL_IFC_LE
+ bool
+
+config SYS_FSL_PEX_LUT_LE
+ bool
+
menu "Layerscape architecture"
depends on FSL_LSCH2 || FSL_LSCH3
config FSL_LAYERSCAPE
bool
+ select ARM_SMCCC
config HAS_FEATURE_GIC64K_ALIGN
bool
config SYS_FSL_ERRATUM_A009798
bool "Workaround for USB PHY erratum A009798"
-config SYS_FSL_ERRATUM_A050106
- bool "Workaround for USB PHY erratum A050106"
+config SYS_FSL_ERRATUM_A050204
+ bool "Workaround for USB PHY erratum A050204"
help
USB3.0 Receiver needs to enable fixed equalization
for each of PHY instances in an SOC. This is similar
Enable the EMC2305 fan controller for configuration of fan
speed.
-config NXP_ESBC
- bool "NXP_ESBC"
- help
- Enable Freescale Secure Boot feature
-
config QSPI_AHB_INIT
bool "Init the QSPI AHB bus"
help
config FSPI_AHB_EN_4BYTE
bool "Enable 4-byte Fast Read command for AHB mode"
- default n
help
The default setting for FlexSPI AHB bus just supports 3-byte addressing.
But some FlexSPI flash sizes are up to 64MBytes.
config SYS_FSL_HAS_DP_DDR
bool
+ help
+ Defines the SoC has DP-DDR used for DPAA.
+
+config DP_DDR_CTRL
+ int
+ depends on SYS_FSL_HAS_DP_DDR
+ default 2 if ARCH_LS2080A
+
+config DP_DDR_DIMM_SLOTS_PER_CTLR
+ int
+ depends on SYS_FSL_HAS_DP_DDR
+ default 1 if ARCH_LS2080A
+
+config DP_DDR_NUM_CTRLS
+ int
+ depends on SYS_FSL_HAS_DP_DDR
+ default 1 if ARCH_LS2080A
+
+config SYS_DP_DDR_BASE
+ hex
+ depends on SYS_FSL_HAS_DP_DDR
+ default 0x6000000000 if ARCH_LS2080A
+
+config SYS_DP_DDR_BASE_PHY
+ int
+ depends on SYS_FSL_HAS_DP_DDR
+ default 0 if ARCH_LS2080A
+ help
+ DDR controller uses this value as the base address for binding.
+ It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
config SYS_FSL_SRDS_1
bool
menu "Layerscape clock tree configuration"
depends on FSL_LSCH2 || FSL_LSCH3
-config SYS_FSL_CLK
- bool "Enable clock tree initialization"
- default y
-
config CLUSTER_CLK_FREQ
int "Reference clock of core cluster"
depends on ARCH_LS1012A
bool
depends on SYS_FSL_EC1 || SYS_FSL_EC2
-config SPL_LDSCRIPT
- default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
-
config HAS_FSL_XHCI_USB
bool
- default y if ARCH_LS1043A || ARCH_LS1046A
help
- For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
+ For some SoC (such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
pins, select it when the pins are assigned to USB.
config SYS_FSL_BOOTROM_BASE
projects / platform / kernel / u-boot.git / blobdiff