Merge branch 'master' of git://git.denx.de/u-boot

[platform/kernel/u-boot.git] / arch / arm / cpu / armv8 / cache_v8.c

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index c5ec529..b1ea822 100644 (file)
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -12,27 +12,36 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifndef CONFIG_SYS_DCACHE_OFF
-void set_pgtable_section(u64 *page_table, u64 index, u64 section,
-                        u64 memory_type)
+inline void set_pgtable_section(u64 *page_table, u64 index, u64 section,
+                        u64 memory_type, u64 share)
 {
        u64 value;
 
        value = section | PMD_TYPE_SECT | PMD_SECT_AF;
        value |= PMD_ATTRINDX(memory_type);
+       value |= share;
+       page_table[index] = value;
+}
+
+inline void set_pgtable_table(u64 *page_table, u64 index, u64 *table_addr)
+{
+       u64 value;
+
+       value = (u64)table_addr | PMD_TYPE_TABLE;
        page_table[index] = value;
 }
 
 /* to activate the MMU we need to set up virtual memory */
 static void mmu_setup(void)
 {
-       int i, j, el;
        bd_t *bd = gd->bd;
-       u64 *page_table = (u64 *)gd->arch.tlb_addr;
+       u64 *page_table = (u64 *)gd->arch.tlb_addr, i, j;
+       int el;
 
        /* Setup an identity-mapping for all spaces */
        for (i = 0; i < (PGTABLE_SIZE >> 3); i++) {
                set_pgtable_section(page_table, i, i << SECTION_SHIFT,
-                                   MT_DEVICE_NGNRNE);
+                                   MT_DEVICE_NGNRNE, PMD_SECT_NON_SHARE);
        }
 
        /* Setup an identity-mapping for all RAM space */
@@ -42,7 +51,7 @@ static void mmu_setup(void)
                for (j = start >> SECTION_SHIFT;
                     j < end >> SECTION_SHIFT; j++) {
                        set_pgtable_section(page_table, j, j << SECTION_SHIFT,
-                                           MT_NORMAL);
+                                           MT_NORMAL, PMD_SECT_NON_SHARE);
                }
        }
 
@@ -50,15 +59,15 @@ static void mmu_setup(void)
        el = current_el();
        if (el == 1) {
                set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
-                                 TCR_FLAGS | TCR_EL1_IPS_BITS,
+                                 TCR_EL1_RSVD | TCR_FLAGS | TCR_EL1_IPS_BITS,
                                  MEMORY_ATTRIBUTES);
        } else if (el == 2) {
                set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
-                                 TCR_FLAGS | TCR_EL2_IPS_BITS,
+                                 TCR_EL2_RSVD | TCR_FLAGS | TCR_EL2_IPS_BITS,
                                  MEMORY_ATTRIBUTES);
        } else {
                set_ttbr_tcr_mair(el, gd->arch.tlb_addr,
-                                 TCR_FLAGS | TCR_EL3_IPS_BITS,
+                                 TCR_EL3_RSVD | TCR_FLAGS | TCR_EL3_IPS_BITS,
                                  MEMORY_ATTRIBUTES);
        }
        /* enable the mmu */
@@ -139,21 +148,44 @@ int dcache_status(void)
        return (get_sctlr() & CR_C) != 0;
 }
 
-#else  /* CONFIG_SYS_DCACHE_OFF */
+u64 *__weak arch_get_page_table(void) {
+       puts("No page table offset defined\n");
 
-void invalidate_dcache_all(void)
-{
+       return NULL;
 }
 
-void flush_dcache_all(void)
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+                                    enum dcache_option option)
 {
+       u64 *page_table = arch_get_page_table();
+       u64 upto, end;
+
+       if (page_table == NULL)
+               return;
+
+       end = ALIGN(start + size, (1 << MMU_SECTION_SHIFT)) >>
+             MMU_SECTION_SHIFT;
+       start = start >> MMU_SECTION_SHIFT;
+       for (upto = start; upto < end; upto++) {
+               page_table[upto] &= ~PMD_ATTRINDX_MASK;
+               page_table[upto] |= PMD_ATTRINDX(option);
+       }
+       asm volatile("dsb sy");
+       __asm_invalidate_tlb_all();
+       asm volatile("dsb sy");
+       asm volatile("isb");
+       start = start << MMU_SECTION_SHIFT;
+       end = end << MMU_SECTION_SHIFT;
+       flush_dcache_range(start, end);
+       asm volatile("dsb sy");
 }
+#else  /* CONFIG_SYS_DCACHE_OFF */
 
-void invalidate_dcache_range(unsigned long start, unsigned long stop)
+void invalidate_dcache_all(void)
 {
 }
 
-void flush_dcache_range(unsigned long start, unsigned long stop)
+void flush_dcache_all(void)
 {
 }
 
@@ -170,6 +202,11 @@ int dcache_status(void)
        return 0;
 }
 
+void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
+                                    enum dcache_option option)
+{
+}
+
 #endif /* CONFIG_SYS_DCACHE_OFF */
 
 #ifndef CONFIG_SYS_ICACHE_OFF
@@ -225,11 +262,3 @@ void __weak enable_caches(void)
        icache_enable();
        dcache_enable();
 }
-
-/*
- * Flush range from all levels of d-cache/unified-cache
- */
-void flush_cache(unsigned long start, unsigned long size)
-{
-       flush_dcache_range(start, start + size);
-}