Merge branch 'master' of git://git.denx.de/u-boot-sunxi

[platform/kernel/u-boot.git] / arch / arm / cpu / armv8 / Kconfig

diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index 472b2ba..f053603 100644 (file)
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -1,5 +1,16 @@
 if ARM64
 
+config ARMV8_SPL_EXCEPTION_VECTORS
+       bool "Install crash dump exception vectors"
+       depends on SPL
+       default y
+       help
+         The default exception vector table is only used for the crash
+         dump, but still takes quite a lot of space in the image size.
+
+         Say N here if you are running out of code space in the image
+         and want to save some space at the cost of less debugging info.
+
 config ARMV8_MULTIENTRY
         bool "Enable multiple CPUs to enter into U-Boot"
 
@@ -30,8 +41,10 @@ config ARMV8_SPIN_TABLE
          To use this feature, you must do:
            - Specify enable-method = "spin-table" in each CPU node in the
              Device Tree you are using to boot the kernel
-           - Let secondary CPUs in U-Boot (in a board specific manner)
-             before the master CPU jumps to the kernel
+           - Bring secondary CPUs into U-Boot proper in a board specific
+             manner.  This must be done *after* relocation.  Otherwise, the
+             secondary CPUs will spin in unprotected memory area because the
+             master CPU protects the relocated spin code.
 
          U-Boot automatically does:
            - Set "cpu-release-addr" property of each CPU node
@@ -39,16 +52,63 @@ config ARMV8_SPIN_TABLE
            - Reserve the code for the spin-table and the release address
              via a /memreserve/ region in the Device Tree.
 
+menu "ARMv8 secure monitor firmware"
+config ARMV8_SEC_FIRMWARE_SUPPORT
+       bool "Enable ARMv8 secure monitor firmware framework support"
+       select FIT
+       select OF_LIBFDT
+       help
+         This framework is aimed at making secure monitor firmware load
+         process brief.
+         Note: Only FIT format image is supported.
+         You should prepare and provide the below information:
+           - Address of secure firmware.
+           - Address to hold the return address from secure firmware.
+           - Secure firmware FIT image related information.
+             Such as: SEC_FIRMWARE_FIT_IMAGE and SEC_FIRMEWARE_FIT_CNF_NAME
+           - The target exception level that secure monitor firmware will
+             return to.
+
+config SPL_ARMV8_SEC_FIRMWARE_SUPPORT
+       bool "Enable ARMv8 secure monitor firmware framework support for SPL"
+       select SPL_FIT
+       select SPL_OF_LIBFDT
+       help
+         Say Y here to support this framework in SPL phase.
+
+config SEC_FIRMWARE_ARMV8_PSCI
+       bool "PSCI implementation in secure monitor firmware"
+       depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
+       help
+         This config enables the ARMv8 PSCI implementation in secure monitor
+         firmware. This is a private PSCI implementation and different from
+         those implemented under the common ARMv8 PSCI framework.
+
+config ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT
+       bool "ARMv8 secure monitor firmware ERET address byteorder swap"
+       depends on ARMV8_SEC_FIRMWARE_SUPPORT || SPL_ARMV8_SEC_FIRMWARE_SUPPORT
+       help
+         Say Y here when the endianness of the register or memory holding the
+         Secure firmware exception return address is different with core's.
+
+endmenu
+
 config PSCI_RESET
        bool "Use PSCI for reset and shutdown"
        default y
-       depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && !TARGET_LS2080A_EMU && \
+       select ARM_SMCCC if OF_CONTROL
+       depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \
                   !TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
-                  !TARGET_LS2080ARDB && !TARGET_LS1012AQDS && \
+                  !TARGET_LS2080ARDB && !TARGET_LS2080A_EMU && \
+                  !TARGET_LS1088ARDB && !TARGET_LS1088AQDS && \
                   !TARGET_LS1012ARDB && !TARGET_LS1012AFRDM && \
+                  !TARGET_LS1012A2G5RDB && !TARGET_LS1012AQDS && \
+                  !TARGET_LS1012AFRWY && \
                   !TARGET_LS1043ARDB && !TARGET_LS1043AQDS && \
                   !TARGET_LS1046ARDB && !TARGET_LS1046AQDS && \
-                  !ARCH_UNIPHIER && !ARCH_SNAPDRAGON && !TARGET_S32V234EVB
+                  !TARGET_LS2081ARDB && !TARGET_LX2160ARDB && \
+                  !TARGET_LX2160AQDS && \
+                  !ARCH_UNIPHIER && !TARGET_S32V234EVB
        help
          Most armv8 systems have PSCI support enabled in EL3, either through
          ARM Trusted Firmware or other firmware.
@@ -86,6 +146,13 @@ config ARMV8_PSCI_CPUS_PER_CLUSTER
          A value 0 or no definition of it works for single cluster system.
          System with multi-cluster should difine their own exact value.
 
+config ARMV8_EA_EL3_FIRST
+       bool "External aborts and SError interrupt exception are taken in EL3"
+       default n
+       help
+         Exception handling at all exception levels for External Abort and
+         SError interrupt exception are taken in EL3.
+
 if SYS_HAS_ARMV8_SECURE_BASE
 
 config ARMV8_SECURE_BASE