#include <asm/arch/sprd_reg.h>
#include <asm/arch/sci_types.h>
#include <asm/arch/adi_hal_internal.h>
+
+extern void __raw_bits_or(unsigned int v, unsigned int a);
+
/*
REG_AON_APB_BOND_OPT0 ==> romcode set
REG_AON_APB_BOND_OPT1 ==> set it later
* 1 : enable jtag success *
* 0 : enable jtag fail *
*************************************************/
-int sprd_jtag_enable()
+int sprd_jtag_enable(void)
{
if (*((volatile unsigned int *)(REG_AON_APB_BOND_OPT0)) & 1)
{
* 1 : disable jtag success *
* 0 : disable jtag fail *
*************************************************/
-int sprd_jtag_disable()
+int sprd_jtag_disable(void)
{
if (!(*((volatile unsigned int *)(REG_AON_APB_BOND_OPT0)) & 1))
{
}
}
-static void ap_slp_cp_dbg_cfg()
+static void ap_slp_cp_dbg_cfg(void)
{
*((volatile unsigned int *)(REG_AP_AHB_MCU_PAUSE)) |= BIT_MCU_SLEEP_FOLLOW_CA7_EN; //when ap sleep, cp can continue debug
}
-static void ap_cpll_rel_cfg()
+static void ap_cpll_rel_cfg(void)
{
*((volatile unsigned int *)(REG_PMU_APB_CPLL_REL_CFG)) |= BIT_CPLL_AP_SEL;
}
-static void bb_bg_auto_en()
-{
- *((volatile unsigned int *)(REG_AON_APB_RES_REG0)) |= 1<<8;
-}
-
-
-static void ap_close_wpll_en()
+#if 0
+static void ap_close_wpll_en(void)
{
*((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_WPLL_AP_EN;
}
-static void ap_close_cpll_en()
+static void ap_close_cpll_en(void)
{
*((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_CPLL_AP_EN;
}
-static void ap_close_wifipll_en()
+static void ap_close_wifipll_en(void)
{
*((volatile unsigned int *)(REG_PMU_APB_CGM_AP_EN)) &= ~BIT_CGM_WIFIPLL1_AP_EN;
}
+#endif
+#ifndef CONFIG_SPX30G
+static void bb_bg_auto_en(void)
+{
+ *((volatile unsigned int *)(REG_AON_APB_RES_REG0)) |= 1<<8;
+}
-static void bb_ldo_auto_en()
+static void bb_ldo_auto_en(void)
{
*((volatile unsigned int *)(REG_AON_APB_RES_REG0)) |= 1<<9;
-}
+}
+#endif
#ifdef CONFIG_PBINT_7S_RESET_V1
#endif
}
#else
-inline int is_smpl_bootup(void)
+__attribute__ ((gnu_inline))inline int is_smpl_bootup(void)
{
return 0;
}
void pmic_init(void)
{
+#ifndef CONFIG_TIZEN
u32 val;
+#endif
pbint_7s_rst_cfg(CONFIG_7S_RST_MODULE_EN,
CONFIG_7S_RST_SW_MODE,
CONFIG_7S_RST_SHORT_MODE);
#define REBOOT_MODE_MASK (0xFFFFFFF0)
#define REBOOT_MODE_PREFIX (0x12345670)
#define REBOOT_THOR_DOWNLOAD (0x1)
+#define REBOOT_RECOVERY (0x4)
int tizen_reboot_check(void)
{
int inform3 = readl(INFORM3);
if ((inform3 & REBOOT_MODE_MASK) == REBOOT_MODE_PREFIX) {
- if ((inform3 & 0xf) == REBOOT_THOR_DOWNLOAD)
+ if ((inform3 & 0xf) == REBOOT_THOR_DOWNLOAD) {
+ writel(0, INFORM3);
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+int tizen_reboot_recovery_check(void)
+{
+ int inform3 = readl(INFORM3);
+
+ if ((inform3 & REBOOT_MODE_MASK) == REBOOT_MODE_PREFIX) {
+ if ((inform3 & 0xf) == REBOOT_RECOVERY) {
+ writel(0, INFORM3);
return 1;
+ }
}
return 0;
#endif
#define REG32(x) (*((volatile uint32 *)(x)))
-void gpu_clk_auto_gate_disable()
+void gpu_clk_auto_gate_disable(void)
{
REG32(REG_PMU_APB_CGM_GPU_MM_AUTO_GATE_EN) &= ~(0x7F);
}
-void misc_init()
+void misc_init(void)
{
scx35_pmu_reconfig();
ap_slp_cp_dbg_cfg();
}mem_cs_info_t;
PUBLIC int get_dram_cs_number(void)
{
- mem_cs_info_t *cs_info_ptr = 0x1C00;
+ mem_cs_info_t *cs_info_ptr = (mem_cs_info_t *)0x1C00;
return cs_info_ptr->cs_number;
}
PUBLIC int get_dram_cs0_size(void)
{
- mem_cs_info_t *cs_info_ptr = 0x1C00;
+ mem_cs_info_t *cs_info_ptr = (mem_cs_info_t *)0x1C00;
return cs_info_ptr->cs0_size;
}