Merge branch 'u-boot-samsung/master' into 'u-boot-arm/master'

[platform/kernel/u-boot.git] / arch / arm / cpu / armv7 / omap5 / sdram.c

diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 2aae3ef..e2ebab8 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -229,6 +229,17 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
        .is_ma_present  = 0x1
 };
 
+/*
+ * DRA722 EVM EMIF1 CONFIGURATION
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
+       .dmm_lisa_map_0 = 0x0,
+       .dmm_lisa_map_1 = 0x0,
+       .dmm_lisa_map_2 = 0x80600100,
+       .dmm_lisa_map_3 = 0xFF020100,
+       .is_ma_present  = 0x1
+};
+
 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 {
        switch (omap_revision()) {
@@ -245,6 +256,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
                *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
                break;
        case DRA752_ES1_0:
+       case DRA752_ES1_1:
                switch (emif_nr) {
                case 1:
                        *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
@@ -254,6 +266,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
                        break;
                }
                break;
+       case DRA722_ES1_0:
        default:
                *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
        }
@@ -273,8 +286,12 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
                *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
                break;
        case DRA752_ES1_0:
-       default:
+       case DRA752_ES1_1:
                *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
+               break;
+       case DRA722_ES1_0:
+       default:
+               *dmm_lisa_regs = &lisa_map_2G_x_2;
        }
 
 }
@@ -460,6 +477,8 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
                *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
                break;
        case DRA752_ES1_0:
+       case DRA752_ES1_1:
+       case DRA722_ES1_0:
                if (emif_nr == 1) {
                        *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
                        *size =
@@ -569,6 +588,76 @@ static const struct lpddr2_device_timings dev_4G_S4_timings = {
        .min_tck        = &min_tck,
 };
 
+/*
+ * List of status registers to be controlled back to control registers
+ * after initial leveling
+ * readreg, writereg
+ */
+const struct read_write_regs omap5_bug_00339_regs[] = {
+       { 8,  5 },
+       { 9,  6 },
+       { 10, 7 },
+       { 14, 8 },
+       { 15, 9 },
+       { 16, 10 },
+       { 11, 2 },
+       { 12, 3 },
+       { 13, 4 },
+       { 17, 11 },
+       { 18, 12 },
+       { 19, 13 },
+};
+
+const struct read_write_regs dra_bug_00339_regs[] = {
+       { 7,  7 },
+       { 8,  8 },
+       { 9,  9 },
+       { 10, 10 },
+       { 11, 11 },
+       { 12, 2 },
+       { 13, 3 },
+       { 14, 4 },
+       { 15, 5 },
+       { 16, 6 },
+       { 17, 12 },
+       { 18, 13 },
+       { 19, 14 },
+       { 20, 15 },
+       { 21, 16 },
+       { 22, 17 },
+       { 23, 18 },
+       { 24, 19 },
+       { 25, 20 },
+       { 26, 21}
+};
+
+const struct read_write_regs *get_bug_regs(u32 *iterations)
+{
+       const struct read_write_regs *bug_00339_regs_ptr = NULL;
+
+       switch (omap_revision()) {
+       case OMAP5430_ES1_0:
+       case OMAP5430_ES2_0:
+       case OMAP5432_ES1_0:
+       case OMAP5432_ES2_0:
+               bug_00339_regs_ptr = omap5_bug_00339_regs;
+               *iterations = sizeof(omap5_bug_00339_regs)/
+                            sizeof(omap5_bug_00339_regs[0]);
+               break;
+       case DRA752_ES1_0:
+       case DRA752_ES1_1:
+       case DRA722_ES1_0:
+               bug_00339_regs_ptr = dra_bug_00339_regs;
+               *iterations = sizeof(dra_bug_00339_regs)/
+                            sizeof(dra_bug_00339_regs[0]);
+               break;
+       default:
+               printf("\n Error: UnKnown SOC");
+       }
+
+       return bug_00339_regs_ptr;
+}
+
 void emif_get_device_timings_sdp(u32 emif_nr,
                const struct lpddr2_device_timings **cs0_device_timings,
                const struct lpddr2_device_timings **cs1_device_timings)