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Merge branch 'master' of git://git.denx.de/u-boot
[platform/kernel/u-boot.git] / arch / arm / cpu / armv7 / omap5 / sdram.c
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 2aae3ef..5f8daa1 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -141,22 +141,23 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .sdram_config_init              = 0x61851ab2,
        .sdram_config                   = 0x61851ab2,
        .sdram_config2                  = 0x08000000,
-       .ref_ctrl                       = 0x00001035,
+       .ref_ctrl                       = 0x000040F1,
+       .ref_ctrl_final                 = 0x00001035,
        .sdram_tim1                     = 0xCCCF36B3,
        .sdram_tim2                     = 0x308F7FDA,
        .sdram_tim3                     = 0x027F88A8,
-       .read_idle_ctrl                 = 0x00050000,
+       .read_idle_ctrl                 = 0x00050001,
        .zq_config                      = 0x0007190B,
        .temp_alert_config              = 0x00000000,
-       .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
-       .emif_ddr_phy_ctlr_1            = 0x0024400A,
+       .emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
+       .emif_ddr_phy_ctlr_1            = 0x0E24400A,
        .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
-       .emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+       .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
+       .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
        .emif_rd_wr_lvl_rmp_win         = 0x00000000,
-       .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+       .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
        .emif_rd_wr_lvl_ctl             = 0x00000000,
        .emif_rd_wr_exec_thresh         = 0x00000305
 };
@@ -165,22 +166,48 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .sdram_config_init              = 0x61851B32,
        .sdram_config                   = 0x61851B32,
        .sdram_config2                  = 0x08000000,
-       .ref_ctrl                       = 0x00001035,
+       .ref_ctrl                       = 0x000040F1,
+       .ref_ctrl_final                 = 0x00001035,
        .sdram_tim1                     = 0xCCCF36B3,
        .sdram_tim2                     = 0x308F7FDA,
        .sdram_tim3                     = 0x027F88A8,
+       .read_idle_ctrl                 = 0x00050001,
+       .zq_config                      = 0x0007190B,
+       .temp_alert_config              = 0x00000000,
+       .emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
+       .emif_ddr_phy_ctlr_1            = 0x0E24400A,
+       .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+       .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
+       .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
+       .emif_rd_wr_lvl_rmp_win         = 0x00000000,
+       .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
+       .emif_rd_wr_lvl_ctl             = 0x00000000,
+       .emif_rd_wr_exec_thresh         = 0x00000305
+};
+
+const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
+       .sdram_config_init              = 0x61862B32,
+       .sdram_config                   = 0x61862B32,
+       .sdram_config2                  = 0x08000000,
+       .ref_ctrl                       = 0x0000493E,
+       .ref_ctrl_final                 = 0x0000144A,
+       .sdram_tim1                     = 0xD113781C,
+       .sdram_tim2                     = 0x308F7FE3,
+       .sdram_tim3                     = 0x009F86A8,
        .read_idle_ctrl                 = 0x00050000,
        .zq_config                      = 0x0007190B,
        .temp_alert_config              = 0x00000000,
-       .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
-       .emif_ddr_phy_ctlr_1            = 0x0024400A,
+       .emif_ddr_phy_ctlr_1_init       = 0x0E24400D,
+       .emif_ddr_phy_ctlr_1            = 0x0E24400D,
        .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
-       .emif_ddr_ext_phy_ctrl_2        = 0x00B000B0,
-       .emif_ddr_ext_phy_ctrl_3        = 0x00B000B0,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
        .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
        .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
        .emif_rd_wr_lvl_rmp_win         = 0x00000000,
-       .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
+       .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
        .emif_rd_wr_lvl_ctl             = 0x00000000,
        .emif_rd_wr_exec_thresh         = 0x00000305
 };
@@ -229,6 +256,17 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
        .is_ma_present  = 0x1
 };
 
+/*
+ * DRA722 EVM EMIF1 CONFIGURATION
+ */
+const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
+       .dmm_lisa_map_0 = 0x0,
+       .dmm_lisa_map_1 = 0x0,
+       .dmm_lisa_map_2 = 0x80600100,
+       .dmm_lisa_map_3 = 0xFF020100,
+       .is_ma_present  = 0x1
+};
+
 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 {
        switch (omap_revision()) {
@@ -245,6 +283,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
                *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
                break;
        case DRA752_ES1_0:
+       case DRA752_ES1_1:
                switch (emif_nr) {
                case 1:
                        *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
@@ -254,6 +293,9 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
                        break;
                }
                break;
+       case DRA722_ES1_0:
+               *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
+               break;
        default:
                *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
        }
@@ -273,8 +315,12 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
                *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
                break;
        case DRA752_ES1_0:
-       default:
+       case DRA752_ES1_1:
                *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
+               break;
+       case DRA722_ES1_0:
+       default:
+               *dmm_lisa_regs = &lisa_map_2G_x_2;
        }
 
 }
@@ -377,24 +423,24 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
 
 const u32
 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
-       0x00B000B0,
-       0x00400040,
-       0x00400040,
-       0x00400040,
-       0x00400040,
-       0x00400040,
-       0x00800080,
-       0x00800080,
-       0x00800080,
-       0x00800080,
-       0x00800080,
-       0x00600060,
-       0x00600060,
-       0x00600060,
-       0x00600060,
-       0x00600060,
-       0x00800080,
-       0x00800080,
+       0x00980098,
+       0x00340034,
+       0x00350035,
+       0x00340034,
+       0x00310031,
+       0x00340034,
+       0x007F007F,
+       0x007F007F,
+       0x007F007F,
+       0x007F007F,
+       0x007F007F,
+       0x00480048,
+       0x004A004A,
+       0x00520052,
+       0x00550055,
+       0x00500050,
+       0x00000000,
+       0x00600020,
        0x40010080,
        0x08102040,
        0x0,
@@ -406,21 +452,50 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
 
 const u32
 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
-       0x00BB00BB,
-       0x00440044,
-       0x00440044,
-       0x00440044,
-       0x00440044,
-       0x00440044,
+       0x00980098,
+       0x00330033,
+       0x00330033,
+       0x002F002F,
+       0x00320032,
+       0x00310031,
        0x007F007F,
        0x007F007F,
        0x007F007F,
        0x007F007F,
        0x007F007F,
-       0x00600060,
-       0x00600060,
-       0x00600060,
-       0x00600060,
+       0x00520052,
+       0x00520052,
+       0x00470047,
+       0x00490049,
+       0x00500050,
+       0x00000000,
+       0x00600020,
+       0x40010080,
+       0x08102040,
+       0x0,
+       0x0,
+       0x0,
+       0x0,
+       0x0
+};
+
+const u32
+dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
+       0x00A400A4,
+       0x00390039,
+       0x00320032,
+       0x00320032,
+       0x00320032,
+       0x00440044,
+       0x00550055,
+       0x00550055,
+       0x00550055,
+       0x00550055,
+       0x007F007F,
+       0x004D004D,
+       0x00430043,
+       0x00560056,
+       0x00540054,
        0x00600060,
        0x0,
        0x00600020,
@@ -441,7 +516,7 @@ const struct lpddr2_mr_regs mr_regs = {
        .mr16   = MR16_REF_FULL_ARRAY
 };
 
-static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
+void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
                                             const u32 **regs,
                                             u32 *size)
 {
@@ -460,6 +535,7 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
                *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
                break;
        case DRA752_ES1_0:
+       case DRA752_ES1_1:
                if (emif_nr == 1) {
                        *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
                        *size =
@@ -470,6 +546,10 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
                        ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
                }
                break;
+       case DRA722_ES1_0:
+               *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
+               *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
+               break;
        default:
                *regs = ddr3_ext_phy_ctrl_const_base_es2;
                *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
@@ -569,6 +649,76 @@ static const struct lpddr2_device_timings dev_4G_S4_timings = {
        .min_tck        = &min_tck,
 };
 
+/*
+ * List of status registers to be controlled back to control registers
+ * after initial leveling
+ * readreg, writereg
+ */
+const struct read_write_regs omap5_bug_00339_regs[] = {
+       { 8,  5 },
+       { 9,  6 },
+       { 10, 7 },
+       { 14, 8 },
+       { 15, 9 },
+       { 16, 10 },
+       { 11, 2 },
+       { 12, 3 },
+       { 13, 4 },
+       { 17, 11 },
+       { 18, 12 },
+       { 19, 13 },
+};
+
+const struct read_write_regs dra_bug_00339_regs[] = {
+       { 7,  7 },
+       { 8,  8 },
+       { 9,  9 },
+       { 10, 10 },
+       { 11, 11 },
+       { 12, 2 },
+       { 13, 3 },
+       { 14, 4 },
+       { 15, 5 },
+       { 16, 6 },
+       { 17, 12 },
+       { 18, 13 },
+       { 19, 14 },
+       { 20, 15 },
+       { 21, 16 },
+       { 22, 17 },
+       { 23, 18 },
+       { 24, 19 },
+       { 25, 20 },
+       { 26, 21}
+};
+
+const struct read_write_regs *get_bug_regs(u32 *iterations)
+{
+       const struct read_write_regs *bug_00339_regs_ptr = NULL;
+
+       switch (omap_revision()) {
+       case OMAP5430_ES1_0:
+       case OMAP5430_ES2_0:
+       case OMAP5432_ES1_0:
+       case OMAP5432_ES2_0:
+               bug_00339_regs_ptr = omap5_bug_00339_regs;
+               *iterations = sizeof(omap5_bug_00339_regs)/
+                            sizeof(omap5_bug_00339_regs[0]);
+               break;
+       case DRA752_ES1_0:
+       case DRA752_ES1_1:
+       case DRA722_ES1_0:
+               bug_00339_regs_ptr = dra_bug_00339_regs;
+               *iterations = sizeof(dra_bug_00339_regs)/
+                            sizeof(dra_bug_00339_regs[0]);
+               break;
+       default:
+               printf("\n Error: UnKnown SOC");
+       }
+
+       return bug_00339_regs_ptr;
+}
+
 void emif_get_device_timings_sdp(u32 emif_nr,
                const struct lpddr2_device_timings **cs0_device_timings,
                const struct lpddr2_device_timings **cs1_device_timings)
Domain: System / Kernel;