Merge branch 'master' of git://git.denx.de/u-boot

[platform/kernel/u-boot.git] / arch / arm / cpu / armv7 / omap5 / sdram.c

diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 065199b..5f8daa1 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -141,7 +141,8 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .sdram_config_init              = 0x61851ab2,
        .sdram_config                   = 0x61851ab2,
        .sdram_config2                  = 0x08000000,
-       .ref_ctrl                       = 0x00001035,
+       .ref_ctrl                       = 0x000040F1,
+       .ref_ctrl_final                 = 0x00001035,
        .sdram_tim1                     = 0xCCCF36B3,
        .sdram_tim2                     = 0x308F7FDA,
        .sdram_tim3                     = 0x027F88A8,
@@ -151,10 +152,10 @@ const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
        .emif_ddr_phy_ctlr_1            = 0x0E24400A,
        .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
-       .emif_ddr_ext_phy_ctrl_2        = 0x00BB00BB,
-       .emif_ddr_ext_phy_ctrl_3        = 0x00BB00BB,
-       .emif_ddr_ext_phy_ctrl_4        = 0x00BB00BB,
-       .emif_ddr_ext_phy_ctrl_5        = 0x00BB00BB,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+       .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
+       .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
        .emif_rd_wr_lvl_rmp_win         = 0x00000000,
        .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
        .emif_rd_wr_lvl_ctl             = 0x00000000,
@@ -165,7 +166,8 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .sdram_config_init              = 0x61851B32,
        .sdram_config                   = 0x61851B32,
        .sdram_config2                  = 0x08000000,
-       .ref_ctrl                       = 0x00001035,
+       .ref_ctrl                       = 0x000040F1,
+       .ref_ctrl_final                 = 0x00001035,
        .sdram_tim1                     = 0xCCCF36B3,
        .sdram_tim2                     = 0x308F7FDA,
        .sdram_tim3                     = 0x027F88A8,
@@ -175,10 +177,10 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
        .emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
        .emif_ddr_phy_ctlr_1            = 0x0E24400A,
        .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
-       .emif_ddr_ext_phy_ctrl_2        = 0x00BB00BB,
-       .emif_ddr_ext_phy_ctrl_3        = 0x00BB00BB,
-       .emif_ddr_ext_phy_ctrl_4        = 0x00BB00BB,
-       .emif_ddr_ext_phy_ctrl_5        = 0x00BB00BB,
+       .emif_ddr_ext_phy_ctrl_2        = 0x00910091,
+       .emif_ddr_ext_phy_ctrl_3        = 0x00950095,
+       .emif_ddr_ext_phy_ctrl_4        = 0x009B009B,
+       .emif_ddr_ext_phy_ctrl_5        = 0x009E009E,
        .emif_rd_wr_lvl_rmp_win         = 0x00000000,
        .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
        .emif_rd_wr_lvl_ctl             = 0x00000000,
@@ -186,18 +188,19 @@ const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
 };
 
 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
-       .sdram_config_init              = 0x61851AB2,
-       .sdram_config                   = 0x61851AB2,
+       .sdram_config_init              = 0x61862B32,
+       .sdram_config                   = 0x61862B32,
        .sdram_config2                  = 0x08000000,
-       .ref_ctrl                       = 0x00001035,
-       .sdram_tim1                     = 0xCCCF36B3,
-       .sdram_tim2                     = 0x308F7FDA,
-       .sdram_tim3                     = 0x027F88A8,
+       .ref_ctrl                       = 0x0000493E,
+       .ref_ctrl_final                 = 0x0000144A,
+       .sdram_tim1                     = 0xD113781C,
+       .sdram_tim2                     = 0x308F7FE3,
+       .sdram_tim3                     = 0x009F86A8,
        .read_idle_ctrl                 = 0x00050000,
        .zq_config                      = 0x0007190B,
        .temp_alert_config              = 0x00000000,
-       .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
-       .emif_ddr_phy_ctlr_1            = 0x0024400A,
+       .emif_ddr_phy_ctlr_1_init       = 0x0E24400D,
+       .emif_ddr_phy_ctlr_1            = 0x0E24400D,
        .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
        .emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
        .emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
@@ -420,22 +423,22 @@ const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
 
 const u32
 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
-       0x00BB00BB,
-       0x00440044,
-       0x00440044,
-       0x00440044,
-       0x00440044,
-       0x00440044,
+       0x00980098,
+       0x00340034,
+       0x00350035,
+       0x00340034,
+       0x00310031,
+       0x00340034,
        0x007F007F,
        0x007F007F,
        0x007F007F,
        0x007F007F,
        0x007F007F,
-       0x00600060,
-       0x00600060,
-       0x00600060,
-       0x00600060,
-       0x00600060,
+       0x00480048,
+       0x004A004A,
+       0x00520052,
+       0x00550055,
+       0x00500050,
        0x00000000,
        0x00600020,
        0x40010080,
@@ -449,22 +452,22 @@ dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
 
 const u32
 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
-       0x00BB00BB,
-       0x00440044,
-       0x00440044,
-       0x00440044,
-       0x00440044,
-       0x00440044,
+       0x00980098,
+       0x00330033,
+       0x00330033,
+       0x002F002F,
+       0x00320032,
+       0x00310031,
        0x007F007F,
        0x007F007F,
        0x007F007F,
        0x007F007F,
        0x007F007F,
-       0x00600060,
-       0x00600060,
-       0x00600060,
-       0x00600060,
-       0x00600060,
+       0x00520052,
+       0x00520052,
+       0x00470047,
+       0x00490049,
+       0x00500050,
        0x00000000,
        0x00600020,
        0x40010080,
@@ -513,7 +516,7 @@ const struct lpddr2_mr_regs mr_regs = {
        .mr16   = MR16_REF_FULL_ARRAY
 };
 
-static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
+void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
                                             const u32 **regs,
                                             u32 *size)
 {