Merge branch 'master' of git://git.denx.de/u-boot-arm

[platform/kernel/u-boot.git] / arch / arm / cpu / armv7 / omap3 / sdrc.c

diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c
index 8905224..6c419f5 100644 (file)
--- a/arch/arm/cpu/armv7/omap3/sdrc.c
+++ b/arch/arm/cpu/armv7/omap3/sdrc.c
@@ -99,7 +99,7 @@ u32 get_sdr_cs_offset(u32 cs)
                return 0;
 
        offset = readl(&sdrc_base->cs_cfg);
-       offset = (offset & 15) << 27 | (offset & 0x30) >> 17;
+       offset = (offset & 15) << 27 | (offset & 0x30) << 17;
 
        return offset;
 }
@@ -163,6 +163,7 @@ void do_sdrc_init(u32 cs, u32 early)
  * dram_init -
  *  - Sets uboots idea of sdram size
  */
+#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
 int dram_init(void)
 {
        DECLARE_GLOBAL_DATA_PTR;
@@ -188,6 +189,43 @@ int dram_init(void)
 
        return 0;
 }
+#else
+int dram_init(void)
+{
+       DECLARE_GLOBAL_DATA_PTR;
+       unsigned int size0 = 0, size1 = 0;
+
+       size0 = get_sdr_cs_size(CS0);
+       /*
+        * If a second bank of DDR is attached to CS1 this is
+        * where it can be started.  Early init code will init
+        * memory on CS0.
+        */
+       if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) {
+               do_sdrc_init(CS1, NOT_EARLY);
+               make_cs1_contiguous();
+
+               size1 = get_sdr_cs_size(CS1);
+       }
+       gd->ram_size = size0 + size1;
+
+       return 0;
+}
+
+void dram_init_banksize (void)
+{
+       DECLARE_GLOBAL_DATA_PTR;
+       unsigned int size0 = 0, size1 = 0;
+
+       size0 = get_sdr_cs_size(CS0);
+       size1 = get_sdr_cs_size(CS1);
+
+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
+       gd->bd->bi_dram[0].size = size0;
+       gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1);
+       gd->bd->bi_dram[1].size = size1;
+}
+#endif
 
 /*
  * mem_init -