SPL: Create arch/arm/lib/spl.c for board_init_f and jump_to_image_linux

[platform/kernel/u-boot.git] / arch / arm / cpu / armv7 / omap3 / board.c

diff --git a/arch/arm/cpu/armv7/omap3/board.c b/arch/arm/cpu/armv7/omap3/board.c
index 1b3ef69..9cee1d9 100644 (file)
--- a/arch/arm/cpu/armv7/omap3/board.c
+++ b/arch/arm/cpu/armv7/omap3/board.c
@@ -33,6 +33,7 @@
  * MA 02111-1307 USA
  */
 #include <common.h>
+#include <spl.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/mem.h>
@@ -40,6 +41,11 @@
 #include <asm/armv7.h>
 #include <asm/arch/gpio.h>
 #include <asm/omap_common.h>
+#include <asm/arch/mmc_host_def.h>
+#include <i2c.h>
+#include <linux/compiler.h>
+
+DECLARE_GLOBAL_DATA_PTR;
 
 /* Declarations */
 extern omap3_sysinfo sysinfo;
@@ -67,40 +73,50 @@ const struct gpio_bank *const omap_gpio_bank = gpio_bank_34xx;
 u32 omap3_boot_device = BOOT_DEVICE_NAND;
 
 /* auto boot mode detection is not possible for OMAP3 - hard code */
-u32 omap_boot_mode(void)
+u32 spl_boot_mode(void)
 {
-       switch (omap_boot_device()) {
+       switch (spl_boot_device()) {
        case BOOT_DEVICE_MMC2:
                return MMCSD_MODE_RAW;
        case BOOT_DEVICE_MMC1:
                return MMCSD_MODE_FAT;
                break;
-       case BOOT_DEVICE_NAND:
-               return NAND_MODE_HW_ECC;
-               break;
        default:
                puts("spl: ERROR:  unknown device - can't select boot mode\n");
                hang();
        }
 }
 
-u32 omap_boot_device(void)
+u32 spl_boot_device(void)
 {
        return omap3_boot_device;
 }
 
-#endif /* CONFIG_SPL_BUILD */
-
+int board_mmc_init(bd_t *bis)
+{
+       switch (spl_boot_device()) {
+       case BOOT_DEVICE_MMC1:
+               omap_mmc_init(0, 0, 0);
+               break;
+       case BOOT_DEVICE_MMC2:
+       case BOOT_DEVICE_MMC2_2:
+               omap_mmc_init(1, 0, 0);
+               break;
+       }
+       return 0;
+}
 
-/******************************************************************************
- * Routine: delay
- * Description: spinning delay to use before udelay works
- *****************************************************************************/
-static inline void delay(unsigned long loops)
+void spl_board_init(void)
 {
-       __asm__ volatile ("1:\n" "subs %0, %1, #1\n"
-                         "bne 1b":"=r" (loops):"0"(loops));
+#ifdef CONFIG_SPL_NAND_SUPPORT
+       gpmc_init();
+#endif
+#ifdef CONFIG_SPL_I2C_SUPPORT
+       i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+#endif
 }
+#endif /* CONFIG_SPL_BUILD */
+
 
 /******************************************************************************
  * Routine: secure_unlock
@@ -149,7 +165,7 @@ void secureworld_exit()
 {
        unsigned long i;
 
-       /* configrue non-secure access control register */
+       /* configure non-secure access control register */
        __asm__ __volatile__("mrc p15, 0, %0, c1, c1, 2":"=r"(i));
        /* enabling co-processor CP10 and CP11 accesses in NS world */
        __asm__ __volatile__("orr %0, %0, #0xC00":"=r"(i));
@@ -227,20 +243,39 @@ void s_init(void)
 #endif
 
        set_muxconf_regs();
-       delay(100);
+       sdelay(100);
 
        prcm_init();
 
        per_clocks_enable();
 
+#ifdef CONFIG_USB_EHCI_OMAP
+       ehci_clocks_enable();
+#endif
+
 #ifdef CONFIG_SPL_BUILD
+       gd = &gdata;
+
        preloader_console_init();
+
+       timer_init();
 #endif
 
        if (!in_sdram)
                mem_init();
 }
 
+/*
+ * Routine: misc_init_r
+ * Description: A basic misc_init_r that just displays the die ID
+ */
+int __weak misc_init_r(void)
+{
+       dieid_num_r();
+
+       return 0;
+}
+
 /******************************************************************************
  * Routine: wait_for_command_complete
  * Description: Wait for posting to finish on watchdog
@@ -392,7 +427,7 @@ static void omap3_setup_aux_cr(void)
 {
        /* Workaround for Cortex-A8 errata: #454179 #430973
         *      Set "IBE" bit
-        *      Set "Disable Brach Size Mispredicts" bit
+        *      Set "Disable Branch Size Mispredicts" bit
         * Workaround for erratum #621766
         *      Enable L1NEON bit
         * ACR |= (IBE | DBSM | L1NEON) => ACR |= 0xE0
@@ -429,7 +464,7 @@ void v7_outer_cache_enable(void)
        omap3_update_aux_cr(0x2, 0);
 }
 
-void v7_outer_cache_disable(void)
+void omap3_outer_cache_disable(void)
 {
        /* Clear L2EN */
        omap3_update_aux_cr_secure(0, 0x2);
@@ -450,9 +485,3 @@ void enable_caches(void)
        dcache_enable();
 }
 #endif
-
-void omap_rev_string(char *omap_rev_string)
-{
-       sprintf(omap_rev_string, "OMAP3, sorry revision detection" \
-               " unimplemented");
-}