*
* Aneesh V <aneesh@ti.com>
*
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/emif.h>
-#include <asm/arch/clocks.h>
+#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <asm/omap_common.h>
#include <asm/utils.h>
return 0;
}
-/*
- * Get SDRAM type connected to EMIF.
- * Assuming similar SDRAM parts are connected to both EMIF's
- * which is typically the case. So it is sufficient to get
- * SDRAM type from EMIF1.
- */
-u32 emif_sdram_type()
-{
- struct emif_reg_struct *emif = (struct emif_reg_struct *)EMIF1_BASE;
-
- return (readl(&emif->emif_sdram_config) &
- EMIF_REG_SDRAM_TYPE_MASK) >> EMIF_REG_SDRAM_TYPE_SHIFT;
-}
-
static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
{
u32 mr;
static void do_lpddr2_init(u32 base, u32 cs)
{
u32 mr_addr;
+ const struct lpddr2_mr_regs *mr_regs;
+ get_lpddr2_mr_regs(&mr_regs);
/* Wait till device auto initialization is complete */
while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
;
- set_mr(base, cs, LPDDR2_MR10, MR10_ZQ_ZQINIT);
+ set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
/*
* tZQINIT = 1 us
* Enough loops assuming a maximum of 2GHz
sdelay(2000);
- if (omap_revision() >= OMAP5430_ES1_0)
- set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8);
- else
- set_mr(base, cs, LPDDR2_MR1, MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3);
-
- set_mr(base, cs, LPDDR2_MR16, MR16_REF_FULL_ARRAY);
+ set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
+ set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
/*
* Enable refresh along with writing MR2
* Encoding of RL in MR2 is (RL - 2)
*/
mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
- set_mr(base, cs, mr_addr, RL_FINAL - 2);
+ set_mr(base, cs, mr_addr, mr_regs->mr2);
- if (omap_revision() >= OMAP5430_ES1_0)
- set_mr(base, cs, LPDDR2_MR3, 0x1);
+ if (mr_regs->mr3 > 0)
+ set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
}
static void lpddr2_init(u32 base, const struct emif_regs *regs)
* un-locked frequency & default RL
*/
writel(regs->sdram_config_init, &emif->emif_sdram_config);
- writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
+ writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
do_ext_phy_settings(base, regs);
writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
- if (omap_revision() >= OMAP5430_ES1_0) {
+ if ((omap_revision() >= OMAP5430_ES1_0) ||
+ (omap_revision() == DRA752_ES1_0)) {
writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
&emif->emif_l3_config);
} else if (omap_revision() >= OMAP4460_ES1_0) {
}
}
-static void ddr3_leveling(u32 base, const struct emif_regs *regs)
+static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
/*
* Set invert_clkout (if activated)--DDR_PHYCTRL_1
- * Invert clock adds an additional half cycle delay on the command
- * interface. The additional half cycle, is usually meant to enable
- * leveling in the situation that DQS is later than CK on the board.It
- * also helps provide some additional margin for leveling.
+ * Invert clock adds an additional half cycle delay on the
+ * command interface. The additional half cycle, is usually
+ * meant to enable leveling in the situation that DQS is later
+ * than CK on the board.It also helps provide some additional
+ * margin for leveling.
*/
- writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
- writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
+ writel(regs->emif_ddr_phy_ctlr_1,
+ &emif->emif_ddr_phy_ctrl_1);
+
+ writel(regs->emif_ddr_phy_ctlr_1,
+ &emif->emif_ddr_phy_ctrl_1_shdw);
__udelay(130);
writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
- & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
+ & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
/* Launch Full leveling */
writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
/* Wait till full leveling is complete */
readl(&emif->emif_rd_wr_lvl_ctl);
- __udelay(130);
+ __udelay(130);
/* Read data eye leveling no of samples */
config_data_eye_leveling_samples(base);
- /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */
- writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl);
+ /*
+ * Launch 8 incremental WR_LVL- to compensate for
+ * PHY limitation.
+ */
+ writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
+ &emif->emif_rd_wr_lvl_ctl);
+
__udelay(130);
/* Launch Incremental leveling */
writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
- __udelay(130);
+ __udelay(130);
+}
+
+static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
+{
+ struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
+
+ u32 fifo_reg;
+
+ fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1);
+ writel(fifo_reg | 0x00000100,
+ &emif->emif_ddr_fifo_misaligned_clear_1);
+
+ fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2);
+ writel(fifo_reg | 0x00000100,
+ &emif->emif_ddr_fifo_misaligned_clear_2);
+
+ /* Launch Full leveling */
+ writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
+
+ /* Wait till full leveling is complete */
+ readl(&emif->emif_rd_wr_lvl_ctl);
+ __udelay(130);
+
+ /* Read data eye leveling no of samples */
+ config_data_eye_leveling_samples(base);
+
+ /*
+ * Disable leveling. This is because if leveling is kept
+ * enabled, then PHY triggers a false leveling during
+ * EMIF-idle scenario which results in wrong delay
+ * values getting updated. After this the EMIF becomes
+ * unaccessible. So disable it after the first time
+ */
+ writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
+}
+
+static void ddr3_leveling(u32 base, const struct emif_regs *regs)
+{
+ if (is_omap54xx())
+ omap5_ddr3_leveling(base, regs);
+ else
+ dra7_ddr3_leveling(base, regs);
}
static void ddr3_init(u32 base, const struct emif_regs *regs)
{
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
- u32 *ext_phy_ctrl_base = 0;
- u32 *emif_ext_phy_ctrl_base = 0;
- u32 i = 0;
/*
* Set SDRAM_CONFIG and PHY control registers to locked frequency
* defined, contents of mode Registers must be fully initialized.
* H/W takes care of this initialization
*/
- writel(regs->sdram_config_init, &emif->emif_sdram_config);
-
writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
/* Update timing registers */
writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
- ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
- emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
-
- /* Configure external phy control timing registers */
- for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
- writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
- }
-
/*
- * external phy 6-24 registers do not change with
- * ddr frequency
+ * The same sequence should work on OMAP5432 as well. But strange that
+ * it is not working
*/
- for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) {
- writel(ddr3_ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
- /* Update shadow registers */
- writel(ddr3_ext_phy_ctrl_const_base[i],
- emif_ext_phy_ctrl_base++);
+ if (omap_revision() == DRA752_ES1_0) {
+ do_ext_phy_settings(base, regs);
+ writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+ writel(regs->sdram_config_init, &emif->emif_sdram_config);
+ } else {
+ writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
+ writel(regs->sdram_config_init, &emif->emif_sdram_config);
+ do_ext_phy_settings(base, regs);
}
/* enable leveling */
return phy;
}
-static u32 get_emif_mem_size(struct emif_device_details *devices)
+static u32 get_emif_mem_size(u32 base)
{
u32 size_mbytes = 0, temp;
+ struct emif_device_details dev_details;
+ struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
+ u32 emif_nr = emif_num(base);
- if (!devices)
- return 0;
+ emif_reset_phy(base);
+ dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
+ &cs0_dev_details);
+ dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
+ &cs1_dev_details);
+ emif_reset_phy(base);
- if (devices->cs0_device_details) {
- temp = devices->cs0_device_details->density;
+ if (dev_details.cs0_device_details) {
+ temp = dev_details.cs0_device_details->density;
size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
}
- if (devices->cs1_device_details) {
- temp = devices->cs1_device_details->density;
+ if (dev_details.cs1_device_details) {
+ temp = dev_details.cs1_device_details->density;
size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
}
/* convert to bytes */
/* Return if no devices on this EMIF */
if (!dev_details.cs0_device_details &&
!dev_details.cs1_device_details) {
- emif_sizes[emif_nr - 1] = 0;
return;
}
- if (!in_sdram)
- emif_sizes[emif_nr - 1] = get_emif_mem_size(&dev_details);
-
/*
* Get device timings:
* - Default timings specified by JESD209-2 if
else
ddr3_init(base, regs);
}
+ if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
+ set_lpmode_selfrefresh(base);
+ emif_reset_phy(base);
+ ddr3_leveling(base, regs);
+ }
/* Write to the shadow registers */
emif_update_timings(base, regs);
struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
u32 omap_rev = omap_revision();
- if (omap_rev == OMAP5430_ES1_0)
- return;
-
/* reset phy on ES2.0 */
if (omap_rev == OMAP4430_ES2_0)
emif_reset_phy(base);
mapped_size = 0;
section_cnt = 3;
sys_addr = CONFIG_SYS_SDRAM_BASE;
- emif1_size = emif_sizes[0];
- emif2_size = emif_sizes[1];
+ emif1_size = get_emif_mem_size(EMIF1_BASE);
+ emif2_size = get_emif_mem_size(EMIF2_BASE);
debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
if (!emif1_size && !emif2_size)
/* TRAP for invalid TILER mappings in section 0 */
lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
+ if (omap_revision() >= OMAP4460_ES1_0)
+ lis_map_regs_calculated.is_ma_present = 1;
+
lisa_map_regs = &lis_map_regs_calculated;
#endif
struct dmm_lisa_map_regs *hw_lisa_map_regs =
writel(lisa_map_regs->dmm_lisa_map_0,
&hw_lisa_map_regs->dmm_lisa_map_0);
- if (omap_revision() >= OMAP4460_ES1_0) {
+ if (lisa_map_regs->is_ma_present) {
hw_lisa_map_regs =
(struct dmm_lisa_map_regs *)MA_BASE;
}
+static void do_bug0039_workaround(u32 base)
+{
+ u32 val, i, clkctrl;
+ struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
+ const struct read_write_regs *bug_00339_regs;
+ u32 iterations;
+ u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
+ u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
+
+ if (is_dra7xx())
+ phy_status_base++;
+
+ bug_00339_regs = get_bug_regs(&iterations);
+
+ /* Put EMIF in to idle */
+ clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
+ __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
+
+ /* Copy the phy status registers in to phy ctrl shadow registers */
+ for (i = 0; i < iterations; i++) {
+ val = __raw_readl(phy_status_base +
+ bug_00339_regs[i].read_reg - 1);
+
+ __raw_writel(val, phy_ctrl_base +
+ ((bug_00339_regs[i].write_reg - 1) << 1));
+
+ __raw_writel(val, phy_ctrl_base +
+ (bug_00339_regs[i].write_reg << 1) - 1);
+ }
+
+ /* Disable leveling */
+ writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
+
+ __raw_writel(clkctrl, (*prcm)->cm_memif_clkstctrl);
+}
+
/*
* SDRAM initialization:
* SDRAM initialization has two parts:
in_sdram = running_from_sdram();
debug("in_sdram = %d\n", in_sdram);
- if (!(in_sdram || warm_reset())) {
- if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
+ if (!in_sdram) {
+ if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
bypass_dpll((*prcm)->cm_clkmode_dpll_core);
- else
+ else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
}
debug("get_ram_size() successful");
}
+ if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
+ (!in_sdram && !warm_reset())) {
+ do_bug0039_workaround(EMIF1_BASE);
+ do_bug0039_workaround(EMIF2_BASE);
+ }
+
debug("<<sdram_init()\n");
}