imx6: clock: Enable External Memory Interface [EIM] clock (eim_slow_clock)

[platform/kernel/u-boot.git] / arch / arm / cpu / armv7 / mx6 / clock.c

diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c
index ff932aa..2995628 100644 (file)
--- a/arch/arm/cpu/armv7/mx6/clock.c
+++ b/arch/arm/cpu/armv7/mx6/clock.c
@@ -7,7 +7,7 @@
 #include <common.h>
 #include <div64.h>
 #include <asm/io.h>
-#include <asm/errno.h>
+#include <linux/errno.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/clock.h>
@@ -97,7 +97,10 @@ void enable_enet_clk(unsigned char enable)
 {
        u32 mask, *addr;
 
-       if (is_mx6ul()) {
+       if (is_mx6ull()) {
+               mask = MXC_CCM_CCGR0_ENET_CLK_ENABLE_MASK;
+               addr = &imx_ccm->CCGR0;
+       } else if (is_mx6ul()) {
                mask = MXC_CCM_CCGR3_ENET_MASK;
                addr = &imx_ccm->CCGR3;
        } else {
@@ -117,7 +120,7 @@ void enable_uart_clk(unsigned char enable)
 {
        u32 mask;
 
-       if (is_mx6ul())
+       if (is_mx6ul() || is_mx6ull())
                mask = MXC_CCM_CCGR5_UART_MASK;
        else
                mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
@@ -168,7 +171,7 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
                        reg &= ~mask;
                __raw_writel(reg, &imx_ccm->CCGR2);
        } else {
-               if (is_mx6sx() || is_mx6ul()) {
+               if (is_mx6sx() || is_mx6ul() || is_mx6ull()) {
                        mask = MXC_CCM_CCGR6_I2C4_MASK;
                        addr = &imx_ccm->CCGR6;
                } else {
@@ -279,9 +282,9 @@ static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num)
 
        switch (pll) {
        case PLL_BUS:
-               if (!is_mx6ul()) {
+               if (!is_mx6ul() && !is_mx6ull()) {
                        if (pfd_num == 3) {
-                               /* No PFD3 on PPL2 */
+                               /* No PFD3 on PLL2 */
                                return 0;
                        }
                }
@@ -380,7 +383,7 @@ static u32 get_ipg_per_clk(void)
 
        reg = __raw_readl(&imx_ccm->cscmr1);
        if (is_mx6sl() || is_mx6sx() ||
-           is_mx6dqp() || is_mx6ul()) {
+           is_mx6dqp() || is_mx6ul() || is_mx6ull()) {
                if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
                        return MXC_HCLK; /* OSC 24Mhz */
        }
@@ -396,7 +399,8 @@ static u32 get_uart_clk(void)
        u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
        reg = __raw_readl(&imx_ccm->cscdr1);
 
-       if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul()) {
+       if (is_mx6sl() || is_mx6sx() || is_mx6dqp() || is_mx6ul() ||
+           is_mx6ull()) {
                if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
                        freq = MXC_HCLK;
        }
@@ -415,7 +419,8 @@ static u32 get_cspi_clk(void)
        cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
                     MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
 
-       if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul()) {
+       if (is_mx6dqp() || is_mx6sl() || is_mx6sx() || is_mx6ul() ||
+           is_mx6ull()) {
                if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
                        return MXC_HCLK / (cspi_podf + 1);
        }
@@ -433,9 +438,9 @@ static u32 get_axi_clk(void)
 
        if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) {
                if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL)
-                       root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
-               else
                        root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1);
+               else
+                       root_freq = mxc_get_pll_pfd(PLL_BUS, 2);
        } else
                root_freq = get_periph_clk();
 
@@ -477,7 +482,7 @@ static u32 get_mmdc_ch0_clk(void)
 
        u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
 
-       if (is_mx6sx() || is_mx6ul() || is_mx6sl()) {
+       if (is_mx6sx() || is_mx6ul() || is_mx6ull() || is_mx6sl()) {
                podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
                        MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
                if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
@@ -615,7 +620,7 @@ void mxs_set_lcdclk(u32 base_addr, u32 freq)
 
        debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
 
-       if (!is_mx6sx() && !is_mx6ul()) {
+       if (!is_mx6sx() && !is_mx6ul() && !is_mx6ull()) {
                debug("This chip not support lcd!\n");
                return;
        }
@@ -749,7 +754,7 @@ int enable_lcdif_clock(u32 base_addr)
                         MXC_CCM_CCGR3_DISP_AXI_MASK) :
                        (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
                         MXC_CCM_CCGR3_DISP_AXI_MASK);
-       } else if (is_mx6ul()) {
+       } else if (is_mx6ul() || is_mx6ull()) {
                if (base_addr != LCDIF1_BASE_ADDR) {
                        puts("Wrong LCD interface!\n");
                        return -EINVAL;
@@ -847,7 +852,7 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
                reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
        } else if (fec_id == 1) {
                /* Only i.MX6SX/UL support ENET2 */
-               if (!(is_mx6sx() || is_mx6ul()))
+               if (!(is_mx6sx() || is_mx6ul() || is_mx6ull()))
                        return -EINVAL;
                reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
                reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
@@ -876,6 +881,11 @@ int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
        writel(reg, &anatop->pll_enet);
 
 #ifdef CONFIG_MX6SX
+       /* Disable enet system clcok before switching clock parent */
+       reg = readl(&imx_ccm->CCGR3);
+       reg &= ~MXC_CCM_CCGR3_ENET_MASK;
+       writel(reg, &imx_ccm->CCGR3);
+
        /*
         * Set enet ahb clock to 200MHz
         * pll2_pfd2_396m-> ENET_PODF-> ENET_AHB
@@ -1069,17 +1079,27 @@ void hab_caam_clock_enable(unsigned char enable)
 {
        u32 reg;
 
-       /* CG4 ~ CG6, CAAM clocks */
-       reg = __raw_readl(&imx_ccm->CCGR0);
-       if (enable)
-               reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
-                       MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
-                       MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
-       else
-               reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
-                       MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
-                       MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
-       __raw_writel(reg, &imx_ccm->CCGR0);
+       if (is_mx6ull()) {
+               /* CG5, DCP clock */
+               reg = __raw_readl(&imx_ccm->CCGR0);
+               if (enable)
+                       reg |= MXC_CCM_CCGR0_DCP_CLK_MASK;
+               else
+                       reg &= ~MXC_CCM_CCGR0_DCP_CLK_MASK;
+               __raw_writel(reg, &imx_ccm->CCGR0);
+       } else {
+               /* CG4 ~ CG6, CAAM clocks */
+               reg = __raw_readl(&imx_ccm->CCGR0);
+               if (enable)
+                       reg |= (MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+                               MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+                               MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+               else
+                       reg &= ~(MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK |
+                               MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK |
+                               MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK);
+               __raw_writel(reg, &imx_ccm->CCGR0);
+       }
 
        /* EMI slow clk */
        reg = __raw_readl(&imx_ccm->CCGR6);
@@ -1364,6 +1384,20 @@ void select_ldb_di_clock_source(enum ldb_di_clock clk)
 }
 #endif
 
+#ifndef CONFIG_SYS_NO_FLASH
+void enable_eim_clk(unsigned char enable)
+{
+       u32 reg;
+
+       reg = __raw_readl(&imx_ccm->CCGR6);
+       if (enable)
+               reg |= MXC_CCM_CCGR6_EMI_SLOW_MASK;
+       else
+               reg &= ~MXC_CCM_CCGR6_EMI_SLOW_MASK;
+       __raw_writel(reg, &imx_ccm->CCGR6);
+}
+#endif
+
 /***************************************************/
 
 U_BOOT_CMD(