PLL_BUS, /* System Bus PLL*/
PLL_USBOTG, /* OTG USB PLL */
PLL_ENET, /* ENET PLL */
+ PLL_AUDIO, /* AUDIO PLL */
+ PLL_VIDEO, /* AUDIO PLL */
};
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
+#if defined(CONFIG_MX6SX)
+ clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
+
+ clrsetbits_le32(&imx_ccm->cs2cdr,
+ MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
+ cfg);
+
+ setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
+#else
clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
clrsetbits_le32(&imx_ccm->cs2cdr,
cfg);
setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
+#endif
setbits_le32(&imx_ccm->CCGR4,
MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
#if defined(CONFIG_FEC_MXC) && !defined(CONFIG_MX6SX)
void enable_enet_clk(unsigned char enable)
{
- u32 mask = MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK;
+ u32 mask, *addr;
+
+ if (is_cpu_type(MXC_CPU_MX6UL)) {
+ mask = MXC_CCM_CCGR3_ENET_MASK;
+ addr = &imx_ccm->CCGR3;
+ } else {
+ mask = MXC_CCM_CCGR1_ENET_MASK;
+ addr = &imx_ccm->CCGR1;
+ }
if (enable)
- setbits_le32(&imx_ccm->CCGR1, mask);
+ setbits_le32(addr, mask);
else
- clrbits_le32(&imx_ccm->CCGR1, mask);
+ clrbits_le32(addr, mask);
}
#endif
#ifdef CONFIG_MXC_UART
void enable_uart_clk(unsigned char enable)
{
- u32 mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
-
- if (enable)
- setbits_le32(&imx_ccm->CCGR5, mask);
- else
- clrbits_le32(&imx_ccm->CCGR5, mask);
-}
-#endif
-
-#ifdef CONFIG_SPI
-/* spi_num can be from 0 - 4 */
-int enable_cspi_clock(unsigned char enable, unsigned spi_num)
-{
u32 mask;
- if (spi_num > 4)
- return -EINVAL;
+ if (is_cpu_type(MXC_CPU_MX6UL))
+ mask = MXC_CCM_CCGR5_UART_MASK;
+ else
+ mask = MXC_CCM_CCGR5_UART_MASK | MXC_CCM_CCGR5_UART_SERIAL_MASK;
- mask = MXC_CCM_CCGR_CG_MASK << (spi_num * 2);
if (enable)
- setbits_le32(&imx_ccm->CCGR1, mask);
+ setbits_le32(&imx_ccm->CCGR5, mask);
else
- clrbits_le32(&imx_ccm->CCGR1, mask);
-
- return 0;
+ clrbits_le32(&imx_ccm->CCGR5, mask);
}
#endif
#endif
#ifdef CONFIG_SYS_I2C_MXC
-/* i2c_num can be from 0 - 2 */
+/* i2c_num can be from 0 - 3 */
int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
{
u32 reg;
u32 mask;
+ u32 *addr;
- if (i2c_num > 2)
+ if (i2c_num > 3)
return -EINVAL;
-
- mask = MXC_CCM_CCGR_CG_MASK
- << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET + (i2c_num << 1));
- reg = __raw_readl(&imx_ccm->CCGR2);
- if (enable)
- reg |= mask;
- else
- reg &= ~mask;
- __raw_writel(reg, &imx_ccm->CCGR2);
+ if (i2c_num < 3) {
+ mask = MXC_CCM_CCGR_CG_MASK
+ << (MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET
+ + (i2c_num << 1));
+ reg = __raw_readl(&imx_ccm->CCGR2);
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ __raw_writel(reg, &imx_ccm->CCGR2);
+ } else {
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
+ mask = MXC_CCM_CCGR6_I2C4_MASK;
+ addr = &imx_ccm->CCGR6;
+ } else {
+ mask = MXC_CCM_CCGR1_I2C4_SERIAL_MASK;
+ addr = &imx_ccm->CCGR1;
+ }
+ reg = __raw_readl(addr);
+ if (enable)
+ reg |= mask;
+ else
+ reg &= ~mask;
+ __raw_writel(reg, addr);
+ }
return 0;
}
#endif
}
static u32 decode_pll(enum pll_clocks pll, u32 infreq)
{
- u32 div;
+ u32 div, test_div, pll_num, pll_denom;
switch (pll) {
case PLL_SYS:
div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
return 25000000 * (div + (div >> 1) + 1);
+ case PLL_AUDIO:
+ div = __raw_readl(&imx_ccm->analog_pll_audio);
+ if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
+ return 0;
+ /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
+ if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
+ return MXC_HCLK;
+ pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
+ pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
+ test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
+ BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
+ div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
+ if (test_div == 3) {
+ debug("Error test_div\n");
+ return 0;
+ }
+ test_div = 1 << (2 - test_div);
+
+ return infreq * (div + pll_num / pll_denom) / test_div;
+ case PLL_VIDEO:
+ div = __raw_readl(&imx_ccm->analog_pll_video);
+ if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
+ return 0;
+ /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
+ if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
+ return MXC_HCLK;
+ pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
+ pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
+ test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
+ BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
+ div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
+ if (test_div == 3) {
+ debug("Error test_div\n");
+ return 0;
+ }
+ test_div = 1 << (2 - test_div);
+
+ return infreq * (div + pll_num / pll_denom) / test_div;
default:
return 0;
}
switch (pll) {
case PLL_BUS:
- if (pfd_num == 3) {
- /* No PFD3 on PPL2 */
- return 0;
+ if (!is_cpu_type(MXC_CPU_MX6UL)) {
+ if (pfd_num == 3) {
+ /* No PFD3 on PPL2 */
+ return 0;
+ }
}
div = __raw_readl(&imx_ccm->analog_pfd_528);
freq = (u64)decode_pll(PLL_BUS, MXC_HCLK);
u32 get_periph_clk(void)
{
- u32 reg, freq = 0;
+ u32 reg, div = 0, freq = 0;
reg = __raw_readl(&imx_ccm->cbcdr);
if (reg & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
+ div = (reg & MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >>
+ MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET;
reg = __raw_readl(&imx_ccm->cbcmr);
reg &= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK;
reg >>= MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET;
}
}
- return freq;
+ return freq / (div + 1);
}
static u32 get_ipg_clk(void)
u32 reg, perclk_podf;
reg = __raw_readl(&imx_ccm->cscmr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
- if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
- return MXC_HCLK; /* OSC 24Mhz */
-#endif
+ if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
+ is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
+ if (reg & MXC_CCM_CSCMR1_PER_CLK_SEL_MASK)
+ return MXC_HCLK; /* OSC 24Mhz */
+ }
+
perclk_podf = reg & MXC_CCM_CSCMR1_PERCLK_PODF_MASK;
return get_ipg_clk() / (perclk_podf + 1);
u32 reg, uart_podf;
u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */
reg = __raw_readl(&imx_ccm->cscdr1);
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
- if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
- freq = MXC_HCLK;
-#endif
+
+ if (is_cpu_type(MXC_CPU_MX6SL) || is_cpu_type(MXC_CPU_MX6SX) ||
+ is_mx6dqp() || is_cpu_type(MXC_CPU_MX6UL)) {
+ if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL)
+ freq = MXC_HCLK;
+ }
+
reg &= MXC_CCM_CSCDR1_UART_CLK_PODF_MASK;
uart_podf = reg >> MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET;
u32 reg, cspi_podf;
reg = __raw_readl(&imx_ccm->cscdr2);
- reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK;
- cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+ cspi_podf = (reg & MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK) >>
+ MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET;
+
+ if (is_mx6dqp() || is_cpu_type(MXC_CPU_MX6SL) ||
+ is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL)) {
+ if (reg & MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK)
+ return MXC_HCLK / (cspi_podf + 1);
+ }
return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1));
}
return root_freq / (emi_slow_podf + 1);
}
-#if (defined(CONFIG_MX6SL) || defined(CONFIG_MX6SX))
static u32 get_mmdc_ch0_clk(void)
{
u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
- u32 freq, podf;
- podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) \
- >> MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
+ u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
+
+ if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
+ is_cpu_type(MXC_CPU_MX6SL)) {
+ podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK) >>
+ MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET;
+ if (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK_SEL) {
+ per2_clk2_podf = (cbcdr & MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK) >>
+ MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET;
+ if (is_cpu_type(MXC_CPU_MX6SL)) {
+ if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
+ freq = MXC_HCLK;
+ else
+ freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ } else {
+ if (cbcmr & MXC_CCM_CBCMR_PERIPH2_CLK2_SEL)
+ freq = decode_pll(PLL_BUS, MXC_HCLK);
+ else
+ freq = decode_pll(PLL_USBOTG, MXC_HCLK);
+ }
+ } else {
+ per2_clk2_podf = 0;
+ switch ((cbcmr &
+ MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
+ MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
+ case 0:
+ freq = decode_pll(PLL_BUS, MXC_HCLK);
+ break;
+ case 1:
+ freq = mxc_get_pll_pfd(PLL_BUS, 2);
+ break;
+ case 2:
+ freq = mxc_get_pll_pfd(PLL_BUS, 0);
+ break;
+ case 3:
+ pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
+ switch (pmu_misc2_audio_div) {
+ case 0:
+ case 2:
+ pmu_misc2_audio_div = 1;
+ break;
+ case 1:
+ pmu_misc2_audio_div = 2;
+ break;
+ case 3:
+ pmu_misc2_audio_div = 4;
+ break;
+ }
+ freq = decode_pll(PLL_AUDIO, MXC_HCLK) /
+ pmu_misc2_audio_div;
+ break;
+ }
+ }
+ return freq / (podf + 1) / (per2_clk2_podf + 1);
+ } else {
+ podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
+ MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
+ return get_periph_clk() / (podf + 1);
+ }
+}
- switch ((cbcmr & MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK) >>
- MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET) {
- case 0:
- freq = decode_pll(PLL_BUS, MXC_HCLK);
- break;
+#if defined(CONFIG_VIDEO_MXS)
+static int enable_pll_video(u32 pll_div, u32 pll_num, u32 pll_denom,
+ u32 post_div)
+{
+ u32 reg = 0;
+ ulong start;
+
+ debug("pll5 div = %d, num = %d, denom = %d\n",
+ pll_div, pll_num, pll_denom);
+
+ /* Power up PLL5 video */
+ writel(BM_ANADIG_PLL_VIDEO_POWERDOWN |
+ BM_ANADIG_PLL_VIDEO_BYPASS |
+ BM_ANADIG_PLL_VIDEO_DIV_SELECT |
+ BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT,
+ &imx_ccm->analog_pll_video_clr);
+
+ /* Set div, num and denom */
+ switch (post_div) {
case 1:
- freq = mxc_get_pll_pfd(PLL_BUS, 2);
+ writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
+ BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x2),
+ &imx_ccm->analog_pll_video_set);
break;
case 2:
- freq = mxc_get_pll_pfd(PLL_BUS, 0);
+ writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
+ BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x1),
+ &imx_ccm->analog_pll_video_set);
break;
- case 3:
- /* static / 2 divider */
- freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
+ case 4:
+ writel(BF_ANADIG_PLL_VIDEO_DIV_SELECT(pll_div) |
+ BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0x0),
+ &imx_ccm->analog_pll_video_set);
+ break;
+ default:
+ puts("Wrong test_div!\n");
+ return -EINVAL;
}
- return freq / (podf + 1);
+ writel(BF_ANADIG_PLL_VIDEO_NUM_A(pll_num),
+ &imx_ccm->analog_pll_video_num);
+ writel(BF_ANADIG_PLL_VIDEO_DENOM_B(pll_denom),
+ &imx_ccm->analog_pll_video_denom);
+
+ /* Wait PLL5 lock */
+ start = get_timer(0); /* Get current timestamp */
+ do {
+ reg = readl(&imx_ccm->analog_pll_video);
+ if (reg & BM_ANADIG_PLL_VIDEO_LOCK) {
+ /* Enable PLL out */
+ writel(BM_ANADIG_PLL_VIDEO_ENABLE,
+ &imx_ccm->analog_pll_video_set);
+ return 0;
+ }
+ } while (get_timer(0) < (start + 10)); /* Wait 10ms */
+
+ puts("Lock PLL5 timeout\n");
+
+ return -ETIME;
}
-#else
-static u32 get_mmdc_ch0_clk(void)
+
+/*
+ * 24M--> PLL_VIDEO -> LCDIFx_PRED -> LCDIFx_PODF -> LCD
+ *
+ * 'freq' using KHz as unit, see driver/video/mxsfb.c.
+ */
+void mxs_set_lcdclk(u32 base_addr, u32 freq)
{
- u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
- u32 mmdc_ch0_podf = (cbcdr & MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK) >>
- MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET;
+ u32 reg = 0;
+ u32 hck = MXC_HCLK / 1000;
+ /* DIV_SELECT ranges from 27 to 54 */
+ u32 min = hck * 27;
+ u32 max = hck * 54;
+ u32 temp, best = 0;
+ u32 i, j, max_pred = 8, max_postd = 8, pred = 1, postd = 1;
+ u32 pll_div, pll_num, pll_denom, post_div = 1;
+
+ debug("mxs_set_lcdclk, freq = %dKHz\n", freq);
+
+ if ((!is_cpu_type(MXC_CPU_MX6SX)) && !is_cpu_type(MXC_CPU_MX6UL)) {
+ debug("This chip not support lcd!\n");
+ return;
+ }
+
+ if (base_addr == LCDIF1_BASE_ADDR) {
+ reg = readl(&imx_ccm->cscdr2);
+ /* Can't change clocks when clock not from pre-mux */
+ if ((reg & MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK) != 0)
+ return;
+ }
+
+ if (is_cpu_type(MXC_CPU_MX6SX)) {
+ reg = readl(&imx_ccm->cscdr2);
+ /* Can't change clocks when clock not from pre-mux */
+ if ((reg & MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK) != 0)
+ return;
+ }
+
+ temp = freq * max_pred * max_postd;
+ if (temp > max) {
+ puts("Please decrease freq, too large!\n");
+ return;
+ }
+ if (temp < min) {
+ /*
+ * Register: PLL_VIDEO
+ * Bit Field: POST_DIV_SELECT
+ * 00 — Divide by 4.
+ * 01 — Divide by 2.
+ * 10 — Divide by 1.
+ * 11 — Reserved
+ * No need to check post_div(1)
+ */
+ for (post_div = 2; post_div <= 4; post_div <<= 1) {
+ if ((temp * post_div) > min) {
+ freq *= post_div;
+ break;
+ }
+ }
+
+ if (post_div > 4) {
+ printf("Fail to set rate to %dkhz", freq);
+ return;
+ }
+ }
+
+ /* Choose the best pred and postd to match freq for lcd */
+ for (i = 1; i <= max_pred; i++) {
+ for (j = 1; j <= max_postd; j++) {
+ temp = freq * i * j;
+ if (temp > max || temp < min)
+ continue;
+ if (best == 0 || temp < best) {
+ best = temp;
+ pred = i;
+ postd = j;
+ }
+ }
+ }
+
+ if (best == 0) {
+ printf("Fail to set rate to %dKHz", freq);
+ return;
+ }
+
+ debug("best %d, pred = %d, postd = %d\n", best, pred, postd);
+
+ pll_div = best / hck;
+ pll_denom = 1000000;
+ pll_num = (best - hck * pll_div) * pll_denom / hck;
+
+ /*
+ * pll_num
+ * (24MHz * (pll_div + --------- ))
+ * pll_denom
+ *freq KHz = --------------------------------
+ * post_div * pred * postd * 1000
+ */
+
+ if (base_addr == LCDIF1_BASE_ADDR) {
+ if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
+ return;
+
+ /* Select pre-lcd clock to PLL5 and set pre divider */
+ clrsetbits_le32(&imx_ccm->cscdr2,
+ MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK |
+ MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK,
+ (0x2 << MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET) |
+ ((pred - 1) <<
+ MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET));
+
+ /* Set the post divider */
+ clrsetbits_le32(&imx_ccm->cbcmr,
+ MXC_CCM_CBCMR_LCDIF1_PODF_MASK,
+ ((postd - 1) <<
+ MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET));
+ } else if (is_cpu_type(MXC_CPU_MX6SX)) {
+ /* Setting LCDIF2 for i.MX6SX */
+ if (enable_pll_video(pll_div, pll_num, pll_denom, post_div))
+ return;
+
+ /* Select pre-lcd clock to PLL5 and set pre divider */
+ clrsetbits_le32(&imx_ccm->cscdr2,
+ MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK |
+ MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK,
+ (0x2 << MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET) |
+ ((pred - 1) <<
+ MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET));
+
+ /* Set the post divider */
+ clrsetbits_le32(&imx_ccm->cscmr1,
+ MXC_CCM_CSCMR1_LCDIF2_PODF_MASK,
+ ((postd - 1) <<
+ MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET));
+ }
+}
+
+int enable_lcdif_clock(u32 base_addr)
+{
+ u32 reg = 0;
+ u32 lcdif_clk_sel_mask, lcdif_ccgr3_mask;
+
+ if (is_cpu_type(MXC_CPU_MX6SX)) {
+ if ((base_addr != LCDIF1_BASE_ADDR) &&
+ (base_addr != LCDIF2_BASE_ADDR)) {
+ puts("Wrong LCD interface!\n");
+ return -EINVAL;
+ }
+ /* Set to pre-mux clock at default */
+ lcdif_clk_sel_mask = (base_addr == LCDIF2_BASE_ADDR) ?
+ MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK :
+ MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
+ lcdif_ccgr3_mask = (base_addr == LCDIF2_BASE_ADDR) ?
+ (MXC_CCM_CCGR3_LCDIF2_PIX_MASK |
+ MXC_CCM_CCGR3_DISP_AXI_MASK) :
+ (MXC_CCM_CCGR3_LCDIF1_PIX_MASK |
+ MXC_CCM_CCGR3_DISP_AXI_MASK);
+ } else if (is_cpu_type(MXC_CPU_MX6UL)) {
+ if (base_addr != LCDIF1_BASE_ADDR) {
+ puts("Wrong LCD interface!\n");
+ return -EINVAL;
+ }
+ /* Set to pre-mux clock at default */
+ lcdif_clk_sel_mask = MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK;
+ lcdif_ccgr3_mask = MXC_CCM_CCGR3_LCDIF1_PIX_MASK;
+ } else {
+ return 0;
+ }
+
+ reg = readl(&imx_ccm->cscdr2);
+ reg &= ~lcdif_clk_sel_mask;
+ writel(reg, &imx_ccm->cscdr2);
+
+ /* Enable the LCDIF pix clock */
+ reg = readl(&imx_ccm->CCGR3);
+ reg |= lcdif_ccgr3_mask;
+ writel(reg, &imx_ccm->CCGR3);
+
+ reg = readl(&imx_ccm->CCGR2);
+ reg |= MXC_CCM_CCGR2_LCD_MASK;
+ writel(reg, &imx_ccm->CCGR2);
+
+ return 0;
+}
+#endif
- return get_periph_clk() / (mmdc_ch0_podf + 1);
+#ifdef CONFIG_FSL_QSPI
+/* qspi_num can be from 0 - 1 */
+void enable_qspi_clk(int qspi_num)
+{
+ u32 reg = 0;
+ /* Enable QuadSPI clock */
+ switch (qspi_num) {
+ case 0:
+ /* disable the clock gate */
+ clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+
+ /* set 50M : (50 = 396 / 2 / 4) */
+ reg = readl(&imx_ccm->cscmr1);
+ reg &= ~(MXC_CCM_CSCMR1_QSPI1_PODF_MASK |
+ MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK);
+ reg |= ((1 << MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET) |
+ (2 << MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET));
+ writel(reg, &imx_ccm->cscmr1);
+
+ /* enable the clock gate */
+ setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);
+ break;
+ case 1:
+ /*
+ * disable the clock gate
+ * QSPI2 and GPMI_BCH_INPUT_GPMI_IO share the same clock gate,
+ * disable both of them.
+ */
+ clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+
+ /* set 50M : (50 = 396 / 2 / 4) */
+ reg = readl(&imx_ccm->cs2cdr);
+ reg &= ~(MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK);
+ reg |= (MXC_CCM_CS2CDR_QSPI2_CLK_PRED(0x1) |
+ MXC_CCM_CS2CDR_QSPI2_CLK_SEL(0x3));
+ writel(reg, &imx_ccm->cs2cdr);
+
+ /*enable the clock gate*/
+ setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |
+ MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK);
+ break;
+ default:
+ break;
+ }
}
#endif
#ifdef CONFIG_FEC_MXC
-int enable_fec_anatop_clock(enum enet_freq freq)
+int enable_fec_anatop_clock(int fec_id, enum enet_freq freq)
{
u32 reg = 0;
s32 timeout = 100000;
struct anatop_regs __iomem *anatop =
(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
- if (freq < ENET_25MHz || freq > ENET_125MHz)
+ if (freq < ENET_25MHZ || freq > ENET_125MHZ)
return -EINVAL;
reg = readl(&anatop->pll_enet);
- reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
- reg |= freq;
+
+ if (fec_id == 0) {
+ reg &= ~BM_ANADIG_PLL_ENET_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_ENET_DIV_SELECT(freq);
+ } else if (fec_id == 1) {
+ /* Only i.MX6SX/UL support ENET2 */
+ if (!(is_cpu_type(MXC_CPU_MX6SX) ||
+ is_cpu_type(MXC_CPU_MX6UL)))
+ return -EINVAL;
+ reg &= ~BM_ANADIG_PLL_ENET2_DIV_SELECT;
+ reg |= BF_ANADIG_PLL_ENET2_DIV_SELECT(freq);
+ } else {
+ return -EINVAL;
+ }
if ((reg & BM_ANADIG_PLL_ENET_POWERDOWN) ||
(!(reg & BM_ANADIG_PLL_ENET_LOCK))) {
}
/* Enable FEC clock */
- reg |= BM_ANADIG_PLL_ENET_ENABLE;
+ if (fec_id == 0)
+ reg |= BM_ANADIG_PLL_ENET_ENABLE;
+ else
+ reg |= BM_ANADIG_PLL_ENET2_ENABLE;
reg &= ~BM_ANADIG_PLL_ENET_BYPASS;
writel(reg, &anatop->pll_enet);
return mxc_get_clock(MXC_IPG_CLK);
}
+#if defined(CONFIG_CMD_SATA) || defined(CONFIG_PCIE_IMX)
static int enable_enet_pll(uint32_t en)
{
struct mxc_ccm_reg *const imx_ccm
writel(reg, &imx_ccm->analog_pll_enet);
return 0;
}
+#endif
-#ifndef CONFIG_MX6SX
+#ifdef CONFIG_CMD_SATA
static void ungate_sata_clock(void)
{
struct mxc_ccm_reg *const imx_ccm =
/* Enable SATA clock. */
setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
}
+
+int enable_sata_clock(void)
+{
+ ungate_sata_clock();
+ return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
+}
+
+void disable_sata_clock(void)
+{
+ struct mxc_ccm_reg *const imx_ccm =
+ (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+
+ clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);
+}
#endif
+#ifdef CONFIG_PCIE_IMX
static void ungate_pcie_clock(void)
{
struct mxc_ccm_reg *const imx_ccm =
setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);
}
-#ifndef CONFIG_MX6SX
-int enable_sata_clock(void)
-{
- ungate_sata_clock();
- return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA);
-}
-#endif
-
int enable_pcie_clock(void)
{
struct anatop_regs *anatop_regs =
clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL);
/* Party time! Ungate the clock to the PCIe. */
-#ifndef CONFIG_MX6SX
+#ifdef CONFIG_CMD_SATA
ungate_sata_clock();
#endif
ungate_pcie_clock();
return enable_enet_pll(BM_ANADIG_PLL_ENET_ENABLE_SATA |
BM_ANADIG_PLL_ENET_ENABLE_PCIE);
}
+#endif
#ifdef CONFIG_SECURE_BOOT
void hab_caam_clock_enable(unsigned char enable)
case MXC_SATA_CLK:
return get_ahb_clk();
default:
+ printf("Unsupported MXC CLK: %d\n", clk);
break;
}
- return -1;
+ return 0;
}
/*
reg = readl(&mxc_ccm->CCGR3);
reg |= MXC_CCM_CCGR3_IPU1_IPU_MASK;
writel(reg, &mxc_ccm->CCGR3);
+
+ if (is_mx6dqp()) {
+ setbits_le32(&mxc_ccm->CCGR6, MXC_CCM_CCGR6_PRG_CLK0_MASK);
+ setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_IPU2_IPU_MASK);
+ }
}
#endif
/***************************************************/