MX53: Handle silicon revision 2.1 case

[kernel/u-boot.git] / arch / arm / cpu / armv7 / mx5 / soc.c

diff --git a/arch/arm/cpu/armv7/mx5/soc.c b/arch/arm/cpu/armv7/mx5/soc.c
index 7c7a565..40b8b56 100644 (file)
--- a/arch/arm/cpu/armv7/mx5/soc.c
+++ b/arch/arm/cpu/armv7/mx5/soc.c
@@ -33,17 +33,20 @@
 #include <fsl_esdhc.h>
 #endif
 
-#if defined(CONFIG_MX51)
-#define CPU_TYPE 0x51000
-#else
+#if !(defined(CONFIG_MX51) || defined(CONFIG_MX53))
 #error "CPU_TYPE not defined"
 #endif
 
 u32 get_cpu_rev(void)
 {
-       int system_rev = CPU_TYPE;
+#ifdef CONFIG_MX51
+       int system_rev = 0x51000;
+#else
+       int system_rev = 0x53000;
+#endif
        int reg = __raw_readl(ROM_SI_REV);
 
+#if defined(CONFIG_MX51)
        switch (reg) {
        case 0x02:
                system_rev |= CHIP_REV_1_1;
@@ -57,14 +60,46 @@ u32 get_cpu_rev(void)
        case 0x20:
                system_rev |= CHIP_REV_3_0;
                break;
-       return system_rev;
        default:
                system_rev |= CHIP_REV_1_0;
                break;
        }
+#else
+       if (reg < 0x20)
+               system_rev |= CHIP_REV_1_0;
+       else
+               system_rev |= reg;
+#endif
        return system_rev;
 }
 
+static char *get_reset_cause(void)
+{
+       u32 cause;
+       struct src *src_regs = (struct src *)SRC_BASE_ADDR;
+
+       cause = readl(&src_regs->srsr);
+       writel(cause, &src_regs->srsr);
+
+       switch (cause) {
+       case 0x00001:
+               return "POR";
+       case 0x00004:
+               return "CSU";
+       case 0x00008:
+               return "IPP USER";
+       case 0x00010:
+               return "WDOG";
+       case 0x00020:
+               return "JTAG HIGH-Z";
+       case 0x00040:
+               return "JTAG SW";
+       case 0x10000:
+               return "WARM BOOT";
+       default:
+               return "unknown reset";
+       }
+}
 
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
@@ -77,6 +112,7 @@ int print_cpuinfo(void)
                (cpurev & 0x000F0) >> 4,
                (cpurev & 0x0000F) >> 0,
                mxc_get_clock(MXC_ARM_CLK) / 1000000);
+       printf("Reset cause: %s\n", get_reset_cause());
        return 0;
 }
 #endif
@@ -100,6 +136,20 @@ int cpu_eth_init(bd_t *bis)
        return rc;
 }
 
+#if defined(CONFIG_FEC_MXC)
+void imx_get_mac_from_fuse(unsigned char *mac)
+{
+       int i;
+       struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
+       struct fuse_bank *bank = &iim->bank[1];
+       struct fuse_bank1_regs *fuse =
+                       (struct fuse_bank1_regs *)bank->fuse_regs;
+
+       for (i = 0; i < 6; i++)
+               mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
+}
+#endif
+
 /*
  * Initializes on-chip MMC controllers.
  * to override, implement board_mmc_init()