.section ".text.init", "x"
+.macro init_arm_erratum
+ /* ARM erratum ID #468414 */
+ mrc 15, 0, r1, c1, c0, 1
+ orr r1, r1, #(1 << 5) /* enable L1NEON bit */
+ mcr 15, 0, r1, c1, c0, 1
+.endm
+
/*
* L2CC Cache setup/invalidation/disable
*/
.endm
.macro init_clock
+#if defined (CONFIG_MX51)
ldr r0, =CCM_BASE_ADDR
-#if defined(CONFIG_MX51)
/* Gate of clocks to the peripherals first */
ldr r1, =0x3FFFFFFF
str r1, [r0, #CLKCTL_CCGR0]
1: ldr r1, [r0, #CLKCTL_CDHIPR]
cmp r1, #0x0
bne 1b
-#else
- ldr r1, =0x3FFFFFFF
- str r1, [r0, #CLKCTL_CCGR0]
- str r4, [r0, #CLKCTL_CCGR1]
- str r4, [r0, #CLKCTL_CCGR2]
- str r4, [r0, #CLKCTL_CCGR3]
- str r4, [r0, #CLKCTL_CCGR7]
-
- ldr r1, =0x00030000
- str r1, [r0, #CLKCTL_CCGR4]
- ldr r1, =0x00FFF030
- str r1, [r0, #CLKCTL_CCGR5]
- ldr r1, =0x0F00030F
- str r1, [r0, #CLKCTL_CCGR6]
-#endif
/* Switch ARM to step clock */
mov r1, #0x4
setup_pll PLL1_BASE_ADDR, 800
#endif
-#if defined(CONFIG_MX51)
setup_pll PLL3_BASE_ADDR, 665
/* Switch peripheral to PLL 3 */
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x000020C0 | CONFIG_SYS_DDR_CLKSEL
str r1, [r0, #CLKCTL_CBCMR]
-#endif
+
setup_pll PLL3_BASE_ADDR, 216
/* Set the platform clock dividers */
ldr r0, =CCM_BASE_ADDR
-#if defined(CONFIG_MX51)
/* Run 3.0 at Full speed, for other TO's wait till we increase VDDGP */
ldr r3, [r4, #ROM_SI_REV]
cmp r3, #0x10
movls r1, #0x1
movhi r1, #0
-#else
- mov r1, #0
-#endif
+
str r1, [r0, #CLKCTL_CACRR]
/* Switch ARM back to PLL 1 */
str r4, [r0, #CLKCTL_CCSR]
-#if defined(CONFIG_MX51)
/* setup the rest */
/* Use lp_apm (24MHz) source for perclk */
ldr r1, =0x000020C2 | CONFIG_SYS_DDR_CLKSEL
/* ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz */
ldr r1, =CONFIG_SYS_CLKTL_CBCDR
str r1, [r0, #CLKCTL_CBCDR]
-#endif
/* Restore the default values in the Gate registers */
ldr r1, =0xFFFFFFFF
str r1, [r0, #CLKCTL_CCGR4]
str r1, [r0, #CLKCTL_CCGR5]
str r1, [r0, #CLKCTL_CCGR6]
-#if defined(CONFIG_MX53)
- str r1, [r0, #CLKCTL_CCGR7]
-#endif
-#if defined(CONFIG_MX51)
/* Use PLL 2 for UART's, get 66.5MHz from it */
ldr r1, =0xA5A2A020
str r1, [r0, #CLKCTL_CSCMR1]
ldr r1, =0x00C30321
str r1, [r0, #CLKCTL_CSCDR1]
-#elif defined(CONFIG_MX53)
+ /* make sure divider effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ str r4, [r0, #CLKCTL_CCDR]
+
+ /* for cko - for ARM div by 8 */
+ mov r1, #0x000A0000
+ add r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
+#else /* CONFIG_MX53 */
+ ldr r0, =CCM_BASE_ADDR
+
+ /* Gate of clocks to the peripherals first */
+ ldr r1, =0x3FFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r4, [r0, #CLKCTL_CCGR1]
+ str r4, [r0, #CLKCTL_CCGR2]
+ str r4, [r0, #CLKCTL_CCGR3]
+ str r4, [r0, #CLKCTL_CCGR7]
+ ldr r1, =0x00030000
+ str r1, [r0, #CLKCTL_CCGR4]
+ ldr r1, =0x00FFF030
+ str r1, [r0, #CLKCTL_CCGR5]
+ ldr r1, =0x0F00030F
+ str r1, [r0, #CLKCTL_CCGR6]
+
+ /* Switch ARM to step clock */
+ mov r1, #0x4
+ str r1, [r0, #CLKCTL_CCSR]
+
+ setup_pll PLL1_BASE_ADDR, 800
+
+ setup_pll PLL3_BASE_ADDR, 400
+
+ /* Switch peripheral to PLL3 */
+ ldr r0, =CCM_BASE_ADDR
+ ldr r1, =0x00015154
+ str r1, [r0, #CLKCTL_CBCMR]
+ ldr r1, =0x02888945
+ orr r1, r1, #(1 << 16)
+ str r1, [r0, #CLKCTL_CBCDR]
+ /* make sure change is effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ setup_pll PLL2_BASE_ADDR, 400
+
/* Switch peripheral to PLL2 */
ldr r0, =CCM_BASE_ADDR
ldr r1, =0x00808145
- orr r1, r1, #2 << 10
- orr r1, r1, #1 << 19
+ orr r1, r1, #(2 << 10)
+ orr r1, r1, #(0 << 16)
+ orr r1, r1, #(1 << 19)
str r1, [r0, #CLKCTL_CBCDR]
ldr r1, =0x00016154
str r1, [r0, #CLKCTL_CBCMR]
- /* Change uart clk parent to pll2*/
+
+ /*change uart clk parent to pll2*/
ldr r1, [r0, #CLKCTL_CSCMR1]
and r1, r1, #0xfcffffff
orr r1, r1, #0x01000000
str r1, [r0, #CLKCTL_CSCMR1]
+
+ /* make sure change is effective */
+1: ldr r1, [r0, #CLKCTL_CDHIPR]
+ cmp r1, #0x0
+ bne 1b
+
+ setup_pll PLL3_BASE_ADDR, 216
+
+ setup_pll PLL4_BASE_ADDR, 455
+
+ /* Set the platform clock dividers */
+ ldr r0, =ARM_BASE_ADDR
+ ldr r1, =0x00000124
+ str r1, [r0, #0x14]
+
+ ldr r0, =CCM_BASE_ADDR
+ mov r1, #0
+ str r1, [r0, #CLKCTL_CACRR]
+
+ /* Switch ARM back to PLL 1. */
+ mov r1, #0x0
+ str r1, [r0, #CLKCTL_CCSR]
+
+ /* make uart div=6 */
ldr r1, [r0, #CLKCTL_CSCDR1]
and r1, r1, #0xffffffc0
orr r1, r1, #0x0a
str r1, [r0, #CLKCTL_CSCDR1]
-#endif
- /* make sure divider effective */
-1: ldr r1, [r0, #CLKCTL_CDHIPR]
- cmp r1, #0x0
- bne 1b
- str r4, [r0, #CLKCTL_CCDR]
+ /* Restore the default values in the Gate registers */
+ ldr r1, =0xFFFFFFFF
+ str r1, [r0, #CLKCTL_CCGR0]
+ str r1, [r0, #CLKCTL_CCGR1]
+ str r1, [r0, #CLKCTL_CCGR2]
+ str r1, [r0, #CLKCTL_CCGR3]
+ str r1, [r0, #CLKCTL_CCGR4]
+ str r1, [r0, #CLKCTL_CCGR5]
+ str r1, [r0, #CLKCTL_CCGR6]
+ str r1, [r0, #CLKCTL_CCGR7]
- /* for cko - for ARM div by 8 */
- mov r1, #0x000A0000
- add r1, r1, #0x00000F0
- str r1, [r0, #CLKCTL_CCOSR]
+ mov r1, #0x00000
+ str r1, [r0, #CLKCTL_CCDR]
+
+ /* for cko - for ARM div by 8 */
+ mov r1, #0x000A0000
+ add r1, r1, #0x00000F0
+ str r1, [r0, #CLKCTL_CCOSR]
+
+#endif /* CONFIG_MX53 */
.endm
.macro setup_wdog
str r1, [r0, #0x4]
#endif
+ init_arm_erratum
+
init_l2cc
init_aips
W_DP_216: .word DP_OP_216
.word DP_MFD_216
.word DP_MFN_216
+W_DP_400: .word DP_OP_400
+ .word DP_MFD_400
+ .word DP_MFN_400
+W_DP_455: .word DP_OP_455
+ .word DP_MFD_455
+ .word DP_MFN_455
projects / platform / kernel / u-boot.git / blobdiff