Merge tag 'tpm-030822' of https://source.denx.de/u-boot/custodians/u-boot-tpm

[platform/kernel/u-boot.git] / arch / arm / cpu / armv7 / ls102xa / Kconfig

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 9ffb90e..e75a895 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -1,30 +1,40 @@
 config ARCH_LS1021A
        bool
+       select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
+       select SYS_FSL_DDR_BE if SYS_FSL_DDR
+       select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
+       select SYS_FSL_IFC_BE
        select SYS_FSL_ERRATUM_A008378
        select SYS_FSL_ERRATUM_A008407
+       select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR
+       select SYS_FSL_ERRATUM_A008997 if USB
+       select SYS_FSL_ERRATUM_A009008 if USB
        select SYS_FSL_ERRATUM_A009663
+       select SYS_FSL_ERRATUM_A009798 if USB
        select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010315
-       select SYS_FSL_SRDS_1
-       select SYS_HAS_SERDES
-       select SYS_FSL_DDR_BE if SYS_FSL_DDR
-       select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
+       select SYS_FSL_ESDHC_BE
+       select SYS_FSL_HAS_CCI400
        select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
        select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
        select SYS_FSL_HAS_SEC
        select SYS_FSL_SEC_COMPAT_5
        select SYS_FSL_SEC_LE
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
+       select SYS_I2C_MXC
+       imply CMD_PCI
+       imply SCSI
+       imply SCSI_AHCI
 
 menu "LS102xA architecture"
        depends on ARCH_LS1021A
 
 config LS1_DEEP_SLEEP
        bool "Deep sleep"
-       depends on ARCH_LS1021A
 
 config MAX_CPUS
        int "Maximum number of CPUs permitted for LS102xA"
-       depends on ARCH_LS1021A
        default 2
        help
          Set this number to the maximum number of possible CPUs in the SoC.
@@ -33,15 +43,45 @@ config MAX_CPUS
          cores, count the reserved ports. This will allocate enough memory
          in spin table to properly handle all cores.
 
-config SECURE_BOOT
-       bool    "Secure Boot"
+config SYS_CCI400_OFFSET
+       hex "Offset for CCI400 base"
+       depends on SYS_FSL_HAS_CCI400
+       default 0x180000
+       help
+         Offset for CCI400 base.
+         CCI400 base addr = CCSRBAR + CCI400_OFFSET
+
+config SYS_FSL_ERRATUM_A008850
+       bool
+       help
+         Workaround for DDR erratum A008850
+
+config SYS_FSL_ERRATUM_A008997
+       bool
+       help
+         Workaround for USB PHY erratum A008997
+
+config SYS_FSL_ERRATUM_A009007
+       bool
+       help
+         Workaround for USB PHY erratum A009007
+
+config SYS_FSL_ERRATUM_A009008
+       bool
+       help
+         Workaround for USB PHY erratum A009008
+
+config SYS_FSL_ERRATUM_A009798
+       bool
        help
-               Enable Freescale Secure Boot feature. Normally selected
-               by defconfig. If unsure, do not change.
+         Workaround for USB PHY erratum A009798
 
 config SYS_FSL_ERRATUM_A010315
        bool "Workaround for PCIe erratum A010315"
 
+config SYS_FSL_HAS_CCI400
+       bool
+
 config SYS_FSL_SRDS_1
        bool
 
@@ -53,7 +93,6 @@ config SYS_HAS_SERDES
 
 config SYS_FSL_IFC_BANK_COUNT
        int "Maximum banks of Integrated flash controller"
-       depends on ARCH_LS1021A
        default 8
 
 config SYS_FSL_ERRATUM_A008407