config ARCH_LS1021A
bool
+ select FSL_IFC if !QSPI_BOOT && !SD_BOOT_QSPI
select SYS_FSL_DDR_BE if SYS_FSL_DDR
select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
+ select SYS_FSL_IFC_BE
select SYS_FSL_ERRATUM_A008378
select SYS_FSL_ERRATUM_A008407
- select SYS_FSL_ERRATUM_A008850
- select SYS_FSL_ERRATUM_A008997
- select SYS_FSL_ERRATUM_A009007
- select SYS_FSL_ERRATUM_A009008
+ select SYS_FSL_ERRATUM_A008850 if SYS_FSL_DDR
+ select SYS_FSL_ERRATUM_A008997 if USB
+ select SYS_FSL_ERRATUM_A009008 if USB
select SYS_FSL_ERRATUM_A009663
- select SYS_FSL_ERRATUM_A009798
+ select SYS_FSL_ERRATUM_A009798 if USB
select SYS_FSL_ERRATUM_A009942
select SYS_FSL_ERRATUM_A010315
+ select SYS_FSL_ESDHC_BE
select SYS_FSL_HAS_CCI400
select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
select SYS_FSL_SEC_LE
select SYS_FSL_SRDS_1
select SYS_HAS_SERDES
+ select SYS_I2C_MXC
imply CMD_PCI
imply SCSI
imply SCSI_AHCI
menu "LS102xA architecture"
depends on ARCH_LS1021A
-config FSL_PCIE_COMPAT
- string "PCIe compatible of Kernel DT"
- depends on PCIE_LAYERSCAPE
- default "fsl,ls1021a-pcie" if ARCH_LS1021A
- help
- This compatible is used to find pci controller node in Kernel DT
- to complete fixup.
-
config LS1_DEEP_SLEEP
bool "Deep sleep"
- depends on ARCH_LS1021A
config MAX_CPUS
int "Maximum number of CPUs permitted for LS102xA"
- depends on ARCH_LS1021A
default 2
help
Set this number to the maximum number of possible CPUs in the SoC.
cores, count the reserved ports. This will allocate enough memory
in spin table to properly handle all cores.
-config SECURE_BOOT
- bool "Secure Boot"
- help
- Enable Freescale Secure Boot feature. Normally selected
- by defconfig. If unsure, do not change.
-
config SYS_CCI400_OFFSET
hex "Offset for CCI400 base"
depends on SYS_FSL_HAS_CCI400
config SYS_FSL_IFC_BANK_COUNT
int "Maximum banks of Integrated flash controller"
- depends on ARCH_LS1021A
default 8
config SYS_FSL_ERRATUM_A008407