Merge git://git.denx.de/u-boot-dm

[platform/kernel/u-boot.git] / arch / arm / cpu / armv7 / ls102xa / Kconfig

diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 920eb4a..6a013b2 100644 (file)
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -1,6 +1,71 @@
 config ARCH_LS1021A
-       bool "Freescale Layerscape LS1021A SoC"
+       bool
+       select SYS_FSL_ERRATUM_A008378
+       select SYS_FSL_ERRATUM_A008407
+       select SYS_FSL_ERRATUM_A009663
+       select SYS_FSL_ERRATUM_A009942
        select SYS_FSL_ERRATUM_A010315
+       select SYS_FSL_SRDS_1
+       select SYS_HAS_SERDES
+       select SYS_FSL_DDR_BE if SYS_FSL_DDR
+       select SYS_FSL_DDR_VER_50 if SYS_FSL_DDR
+       select SYS_FSL_HAS_DDR3 if SYS_FSL_DDR
+       select SYS_FSL_HAS_DDR4 if SYS_FSL_DDR
+       select SYS_FSL_HAS_SEC
+       select SYS_FSL_SEC_COMPAT_5
+       select SYS_FSL_SEC_LE
+       imply SCSI
+
+menu "LS102xA architecture"
+       depends on ARCH_LS1021A
+
+config FSL_PCIE_COMPAT
+       string "PCIe compatible of Kernel DT"
+       depends on PCIE_LAYERSCAPE
+       default "fsl,ls1021a-pcie" if ARCH_LS1021A
+       help
+         This compatible is used to find pci controller node in Kernel DT
+         to complete fixup.
 
 config LS1_DEEP_SLEEP
-       bool "Freescale Layerscape 1 deep sleep"
+       bool "Deep sleep"
+       depends on ARCH_LS1021A
+
+config MAX_CPUS
+       int "Maximum number of CPUs permitted for LS102xA"
+       depends on ARCH_LS1021A
+       default 2
+       help
+         Set this number to the maximum number of possible CPUs in the SoC.
+         SoCs may have multiple clusters with each cluster may have multiple
+         ports. If some ports are reserved but higher ports are used for
+         cores, count the reserved ports. This will allocate enough memory
+         in spin table to properly handle all cores.
+
+config SECURE_BOOT
+       bool    "Secure Boot"
+       help
+               Enable Freescale Secure Boot feature. Normally selected
+               by defconfig. If unsure, do not change.
+
+config SYS_FSL_ERRATUM_A010315
+       bool "Workaround for PCIe erratum A010315"
+
+config SYS_FSL_SRDS_1
+       bool
+
+config SYS_FSL_SRDS_2
+       bool
+
+config SYS_HAS_SERDES
+       bool
+
+config SYS_FSL_IFC_BANK_COUNT
+       int "Maximum banks of Integrated flash controller"
+       depends on ARCH_LS1021A
+       default 8
+
+config SYS_FSL_ERRATUM_A008407
+       bool
+
+endmenu