Merge branch 'master' of git://git.denx.de/u-boot-socfpga

[platform/kernel/u-boot.git] / arch / arm / cpu / armv7 / bcm281xx / clk-bcm281xx.c

diff --git a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
index bc8a170..7e25255 100644 (file)
--- a/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
+++ b/arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c
@@ -118,6 +118,16 @@ unsigned long slave_apb_freq_tbl[8] = {
        78 * CLOCK_1M
 };
 
+unsigned long esub_freq_tbl[8] = {
+       78 * CLOCK_1M,
+       156 * CLOCK_1M,
+       156 * CLOCK_1M,
+       156 * CLOCK_1M,
+       208 * CLOCK_1M,
+       208 * CLOCK_1M,
+       208 * CLOCK_1M
+};
+
 static struct bus_clk_data bsc1_apb_data = {
        .gate = HW_SW_GATE_AUTO(0x0458, 16, 0, 1),
 };
@@ -199,6 +209,10 @@ static struct peri_clk_data sdio4_sleep_data = {
        .gate           = SW_ONLY_GATE(0x0360, 20, 4),
 };
 
+static struct bus_clk_data usb_otg_ahb_data = {
+       .gate           = HW_SW_GATE_AUTO(0x0348, 16, 0, 1),
+};
+
 static struct bus_clk_data sdio1_ahb_data = {
        .gate           = HW_SW_GATE_AUTO(0x0358, 16, 0, 1),
 };
@@ -295,11 +309,43 @@ static struct ccu_clock kps_ccu_clk = {
        .freq_tbl = slave_axi_freq_tbl,
 };
 
+#ifdef CONFIG_BCM_SF2_ETH
+static struct ccu_clock esub_ccu_clk = {
+       .clk = {
+               .name = "esub_ccu_clk",
+               .ops = &ccu_clk_ops,
+               .ccu_clk_mgr_base = ESUB_CLK_BASE_ADDR,
+       },
+       .num_policy_masks = 1,
+       .policy_freq_offset = 0x00000008,
+       .freq_bit_shift = 8,
+       .policy_ctl_offset = 0x0000000c,
+       .policy0_mask_offset = 0x00000010,
+       .policy1_mask_offset = 0x00000014,
+       .policy2_mask_offset = 0x00000018,
+       .policy3_mask_offset = 0x0000001c,
+       .lvm_en_offset = 0x00000034,
+       .freq_id = 2,
+       .freq_tbl = esub_freq_tbl,
+};
+#endif
+
 /*
  * Bus clocks
  */
 
 /* KPM bus clocks */
+static struct bus_clock usb_otg_ahb_clk = {
+       .clk = {
+               .name = "usb_otg_ahb_clk",
+               .parent = &kpm_ccu_clk.clk,
+               .ops = &bus_clk_ops,
+               .ccu_clk_mgr_base = KONA_MST_CLK_BASE_ADDR,
+       },
+       .freq_tbl = master_ahb_freq_tbl,
+       .data = &usb_otg_ahb_data,
+};
+
 static struct bus_clock sdio1_ahb_clk = {
        .clk = {
                .name = "sdio1_ahb_clk",
@@ -510,6 +556,7 @@ struct clk_lookup arch_clk_tbl[] = {
        CLK_LK(bsc2),
        CLK_LK(bsc3),
        /* Bus clocks */
+       CLK_LK(usb_otg_ahb),
        CLK_LK(sdio1_ahb),
        CLK_LK(sdio2_ahb),
        CLK_LK(sdio3_ahb),
@@ -517,6 +564,9 @@ struct clk_lookup arch_clk_tbl[] = {
        CLK_LK(bsc1_apb),
        CLK_LK(bsc2_apb),
        CLK_LK(bsc3_apb),
+#ifdef CONFIG_BCM_SF2_ETH
+       CLK_LK(esub_ccu),
+#endif
 };
 
 /* public array size */