*/
#include <common.h>
+#include <errno.h>
+#include <spl.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
+#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
+#include <asm/arch/gpio.h>
+#include <asm/arch/mmc_host_def.h>
+#include <asm/arch/sys_proto.h>
#include <asm/io.h>
+#include <asm/emif.h>
+#include <asm/gpio.h>
+#include <i2c.h>
+#include <miiphy.h>
+#include <cpsw.h>
DECLARE_GLOBAL_DATA_PTR;
-struct wd_timer *wdtimer = (struct wd_timer *)WDT_BASE;
-struct timer_reg *timerreg = (struct timer_reg *)DM_TIMER2_BASE;
+static const struct gpio_bank gpio_bank_am33xx[4] = {
+ { (void *)AM33XX_GPIO0_BASE, METHOD_GPIO_24XX },
+ { (void *)AM33XX_GPIO1_BASE, METHOD_GPIO_24XX },
+ { (void *)AM33XX_GPIO2_BASE, METHOD_GPIO_24XX },
+ { (void *)AM33XX_GPIO3_BASE, METHOD_GPIO_24XX },
+};
-/*
- * early system init of muxing and clocks.
- */
-void s_init(u32 in_ddr)
+const struct gpio_bank *const omap_gpio_bank = gpio_bank_am33xx;
+
+#if defined(CONFIG_OMAP_HSMMC) && !defined(CONFIG_SPL_BUILD)
+int cpu_mmc_init(bd_t *bis)
{
- /* WDT1 is already running when the bootloader gets control
- * Disable it to avoid "random" resets
- */
- writel(0xAAAA, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
- writel(0x5555, &wdtimer->wdtwspr);
- while (readl(&wdtimer->wdtwwps) != 0x0)
- ;
+ int ret;
- /* Setup the PLLs and the clocks for the peripherals */
-#ifdef CONFIG_SETUP_PLL
- pll_init();
-#endif
- if (!in_ddr)
- config_ddr();
+ ret = omap_mmc_init(0, 0, 0);
+ if (ret)
+ return ret;
+
+ return omap_mmc_init(1, 0, 0);
}
+#endif
-/* Initialize timer */
-void init_timer(void)
+void setup_clocks_for_console(void)
{
- /* Reset the Timer */
- writel(0x2, (&timerreg->tsicrreg));
-
- /* Wait until the reset is done */
- while (readl(&timerreg->tiocpcfgreg) & 1)
- ;
-
- /* Start the Timer */
- writel(0x1, (&timerreg->tclrreg));
+ /* Not yet implemented */
+ return;
}