warp: Add initial WaRP Board support

[platform/kernel/u-boot.git] / arch / arm / cpu / arm926ejs / pantheon / cpu.c

diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
index 8b2eafa..4e2a177 100644 (file)
--- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c
+++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
@@ -3,28 +3,12 @@
  * Marvell Semiconductor <www.marvell.com>
  * Written-by: Lei Wen <leiwen@marvell.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301 USA
+ * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <common.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/pantheon.h>
-#include <asm/io.h>
 
 #define UARTCLK14745KHZ        (APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
 #define SET_MRVL_ID    (1<<8)
@@ -42,6 +26,9 @@ int arch_cpu_init(void)
        struct panthmpmu_registers *mpmu =
                (struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
 
+       struct panthapmu_registers *apmu =
+               (struct panthapmu_registers *) PANTHEON_APMU_BASE;
+
        /* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
        val = readl(&cpuregs->cpu_conf);
        val = val | SET_MRVL_ID;
@@ -65,6 +52,14 @@ int arch_cpu_init(void)
        writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
 #endif
 
+#ifdef CONFIG_MV_SDHCI
+       /* Enable mmc clock */
+       writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
+                       &apmu->sd1);
+       writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
+                       &apmu->sd3);
+#endif
+
        icache_enable();
 
        return 0;