ARM: kirkwood: fix cpu info for 6282 device id

[platform/kernel/u-boot.git] / arch / arm / cpu / arm926ejs / kirkwood / cpu.c

diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index cde3172..4c9d3fd 100644 (file)
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -9,13 +9,10 @@
 #include <common.h>
 #include <netdev.h>
 #include <asm/cache.h>
-#include <u-boot/md5.h>
 #include <asm/io.h>
 #include <asm/arch/cpu.h>
-#include <asm/arch/kirkwood.h>
-#include <hush.h>
-
-#define BUFLEN 16
+#include <asm/arch/soc.h>
+#include <mvebu_mmc.h>
 
 void reset_cpu(unsigned long ignored)
 {
@@ -30,31 +27,6 @@ void reset_cpu(unsigned long ignored)
 }
 
 /*
- * Generates Ramdom hex number reading some time varient system registers
- * and using md5 algorithm
- */
-unsigned char get_random_hex(void)
-{
-       int i;
-       u32 inbuf[BUFLEN];
-       u8 outbuf[BUFLEN];
-
-       /*
-        * in case of 88F6281/88F6282/88F6192 A0,
-        * Bit7 need to reset to generate random values in KW_REG_UNDOC_0x1470
-        * Soc reg offsets KW_REG_UNDOC_0x1470 and KW_REG_UNDOC_0x1478 are
-        * reserved regs and does not have names at this moment
-        * (no errata available)
-        */
-       writel(readl(KW_REG_UNDOC_0x1478) & ~(1 << 7), KW_REG_UNDOC_0x1478);
-       for (i = 0; i < BUFLEN; i++) {
-               inbuf[i] = readl(KW_REG_UNDOC_0x1470);
-       }
-       md5((u8 *) inbuf, (BUFLEN * sizeof(u32)), outbuf);
-       return outbuf[outbuf[7] % 0x0f];
-}
-
-/*
  * Window Size
  * Used with the Base register to set the address window size and location.
  * Must be programmed from LSB to MSB as sequence of ones followed by
@@ -140,50 +112,6 @@ int kw_config_adr_windows(void)
 }
 
 /*
- * kw_config_gpio - GPIO configuration
- */
-void kw_config_gpio(u32 gpp0_oe_val, u32 gpp1_oe_val, u32 gpp0_oe, u32 gpp1_oe)
-{
-       struct kwgpio_registers *gpio0reg =
-               (struct kwgpio_registers *)KW_GPIO0_BASE;
-       struct kwgpio_registers *gpio1reg =
-               (struct kwgpio_registers *)KW_GPIO1_BASE;
-
-       /* Init GPIOS to default values as per board requirement */
-       writel(gpp0_oe_val, &gpio0reg->dout);
-       writel(gpp1_oe_val, &gpio1reg->dout);
-       writel(gpp0_oe, &gpio0reg->oe);
-       writel(gpp1_oe, &gpio1reg->oe);
-}
-
-/*
- * kw_config_mpp - Multi-Purpose Pins Functionality configuration
- *
- * Each MPP can be configured to different functionality through
- * MPP control register, ref (sec 6.1 of kirkwood h/w specification)
- *
- * There are maximum 64 Multi-Pourpose Pins on Kirkwood
- * Each MPP functionality can be configuration by a 4bit value
- * of MPP control reg, the value and associated functionality depends
- * upon used SoC varient
- */
-int kw_config_mpp(u32 mpp0_7, u32 mpp8_15, u32 mpp16_23, u32 mpp24_31,
-               u32 mpp32_39, u32 mpp40_47, u32 mpp48_55)
-{
-       u32 *mppreg = (u32 *) KW_MPP_BASE;
-
-       /* program mpp registers */
-       writel(mpp0_7, &mppreg[0]);
-       writel(mpp8_15, &mppreg[1]);
-       writel(mpp16_23, &mppreg[2]);
-       writel(mpp24_31, &mppreg[3]);
-       writel(mpp32_39, &mppreg[4]);
-       writel(mpp40_47, &mppreg[5]);
-       writel(mpp48_55, &mppreg[6]);
-       return 0;
-}
-
-/*
  * SYSRSTn Duration Counter Support
  *
  * Kirkwood SoC implements a hardware-based SYSRSTn duration counter.
@@ -211,7 +139,7 @@ static void kw_sysrst_action(void)
 
        debug("Starting %s process...\n", __FUNCTION__);
        ret = run_command(s, 0);
-       if (ret < 0)
+       if (ret != 0)
                debug("Error.. %s failed\n", __FUNCTION__);
        else
                debug("%s process finished\n", __FUNCTION__);
@@ -253,7 +181,7 @@ static void kw_sysrst_check(void)
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo(void)
 {
-       char *rev;
+       char *rev = "??";
        u16 devid = (readl(KW_REG_PCIE_DEVID) >> 16) & 0xffff;
        u8 revid = readl(KW_REG_PCIE_REVID) & 0xff;
 
@@ -264,7 +192,13 @@ int print_cpuinfo(void)
 
        switch (revid) {
        case 0:
-               rev = "Z0";
+               if (devid == 0x6281)
+                       rev = "Z0";
+               else if (devid == 0x6282)
+                       rev = "A0";
+               break;
+       case 1:
+               rev = "A1";
                break;
        case 2:
                rev = "A0";
@@ -273,7 +207,6 @@ int print_cpuinfo(void)
                rev = "A1";
                break;
        default:
-               rev = "??";
                break;
        }
 
@@ -302,7 +235,7 @@ int arch_cpu_init(void)
        /*
         * Configures the I/O voltage of the pads connected to Egigabit
         * Ethernet interface to 1.8V
-        * By defult it is set to 3.3V
+        * By default it is set to 3.3V
         */
        reg = readl(KW_REG_MPP_OUT_DRV_REG);
        reg |= (1 << 7);
@@ -378,3 +311,11 @@ int cpu_eth_init(bd_t *bis)
        return 0;
 }
 #endif
+
+#ifdef CONFIG_MVEBU_MMC
+int board_mmc_init(bd_t *bis)
+{
+       mvebu_mmc_init(bis);
+       return 0;
+}
+#endif /* CONFIG_MVEBU_MMC */