*
* Copyright (c) 2004 Texas Instruments <r-woodruff2@ti.com>
*
- * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
- * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
+ * Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
+ * Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
* Copyright (c) 2003 Richard Woodruff <r-woodruff2@ti.com>
* Copyright (c) 2003 Kshitij <kshitij@ti.com>
#include <version.h>
.globl _start
_start: b reset
-#ifdef CONFIG_PRELOADER
+#ifdef CONFIG_SPL_BUILD
ldr pc, _hang
ldr pc, _hang
ldr pc, _hang
_irq: .word irq
_fiq: .word fiq
_pad: .word 0x12345678 /* now 16*4=64 */
-#endif /* CONFIG_PRELOADER */
+#endif /* CONFIG_SPL_BUILD */
.global _end_vect
_end_vect:
_bss_start_ofs:
.word __bss_start - _start
+.global _image_copy_end_ofs
+_image_copy_end_ofs:
+ .word __image_copy_end - _start
+
.globl _bss_end_ofs
_bss_end_ofs:
+ .word __bss_end__ - _start
+
+.globl _end_ofs
+_end_ofs:
.word _end - _start
#ifdef CONFIG_USE_IRQ
/* Set stackpointer in internal RAM to call board_init_f */
call_board_init_f:
ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
+ bic sp, sp, #7 /* 8-byte alignment for ABI compliance */
ldr r0,=0x00000000
-#ifdef CONFIG_NAND_SPL
- bl nand_boot
-#else
-#ifdef CONFIG_ONENAND_IPL
- bl start_oneboot
-#else
bl board_init_f
-#endif /* CONFIG_ONENAND_IPL */
-#endif /* CONFIG_NAND_SPL */
/*------------------------------------------------------------------------------*/
mov r4, r0 /* save addr_sp */
mov r5, r1 /* save addr of gd */
mov r6, r2 /* save addr of destination */
- mov r7, r2 /* save addr of destination */
/* Set up the stack */
stack_setup:
mov sp, r4
adr r0, _start
- ldr r2, _TEXT_BASE
- ldr r3, _bss_start_ofs
- add r2, r0, r3 /* r2 <- source end address */
cmp r0, r6
- beq clear_bss
+ moveq r9, #0 /* no relocation. relocation offset(r9) = 0 */
+ beq clear_bss /* skip relocation */
+ mov r1, r6 /* r1 <- scratch for copy_loop */
+ ldr r3, _image_copy_end_ofs
+ add r2, r0, r3 /* r2 <- source end address */
copy_loop:
ldmia r0!, {r9-r10} /* copy from source address [r0] */
- stmia r6!, {r9-r10} /* copy to target address [r1] */
+ stmia r1!, {r9-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
blo copy_loop
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
* fix .rel.dyn relocations
*/
ldr r0, _TEXT_BASE /* r0 <- Text base */
- sub r9, r7, r0 /* r9 <- relocation offset */
+ sub r9, r6, r0 /* r9 <- relocation offset */
ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
add r10, r10, r0 /* r10 <- sym table in FLASH */
ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
add r0, r0, r9 /* r0 <- location to fix up in RAM */
ldr r1, [r2, #4]
- and r8, r1, #0xff
- cmp r8, #23 /* relative fixup? */
+ and r7, r1, #0xff
+ cmp r7, #23 /* relative fixup? */
beq fixrel
- cmp r8, #2 /* absolute fixup? */
+ cmp r7, #2 /* absolute fixup? */
beq fixabs
/* ignore unknown type of fixup */
b fixnext
mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
add r1, r10, r1 /* r1 <- address of symbol in table */
ldr r1, [r1, #4] /* r1 <- symbol value */
- add r1, r9 /* r1 <- relocated sym addr */
+ add r1, r1, r9 /* r1 <- relocated sym addr */
b fixnext
fixrel:
/* relative fix: increase location by offset */
add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
cmp r2, r3
blo fixloop
+ b clear_bss
+
+_rel_dyn_start_ofs:
+ .word __rel_dyn_start - _start
+_rel_dyn_end_ofs:
+ .word __rel_dyn_end - _start
+_dynsym_start_ofs:
+ .word __dynsym_start - _start
#endif
clear_bss:
-#ifndef CONFIG_PRELOADER
+#ifdef CONFIG_SPL_BUILD
+ /* No relocation for SPL */
+ ldr r0, =__bss_start
+ ldr r1, =__bss_end__
+#else
ldr r0, _bss_start_ofs
ldr r1, _bss_end_ofs
- ldr r3, _TEXT_BASE /* Text base */
- mov r4, r7 /* reloc addr */
+ mov r4, r6 /* reloc addr */
add r0, r0, r4
add r1, r1, r4
+#endif
mov r2, #0x00000000 /* clear */
-clbss_l:str r2, [r0] /* clear loop... */
+clbss_l:cmp r0, r1 /* clear loop... */
+ bhs clbss_e /* if reached end of bss, exit */
+ str r2, [r0]
add r0, r0, #4
- cmp r0, r1
- bne clbss_l
-#endif /* #ifndef CONFIG_PRELOADER */
+ b clbss_l
+clbss_e:
/*
* We are done. Do not return, instead branch to second part of board
*/
#ifdef CONFIG_NAND_SPL
ldr r0, _nand_boot_ofs
- adr r1, _start
- add pc, r0, r1
-_nand_boot_ofs
- : .word nand_boot - _start
+ mov pc, r0
+
+_nand_boot_ofs:
+ .word nand_boot
#else
jump_2_ram:
ldr r0, _board_init_r_ofs
add lr, lr, r9
/* setup parameters for board_init_r */
mov r0, r5 /* gd_t */
- mov r1, r7 /* dest_addr */
+ mov r1, r6 /* dest_addr */
/* jump to it ... */
mov pc, lr
.word board_init_r - _start
#endif
-_rel_dyn_start_ofs:
- .word __rel_dyn_start - _start
-_rel_dyn_end_ofs:
- .word __rel_dyn_end - _start
-_dynsym_start_ofs:
- .word __dynsym_start - _start
-
/*
*************************************************************************
*
mov pc, lr /* back to my caller */
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
-#ifndef CONFIG_PRELOADER
+#ifndef CONFIG_SPL_BUILD
/*
*************************************************************************
*
.macro get_fiq_stack @ setup FIQ stack
ldr sp, FIQ_STACK_START
.endm
-#endif /* CONFIG_PRELOADER */
+#endif /* CONFIG_SPL_BUILD */
/*
* exception handlers
*/
-#ifdef CONFIG_PRELOADER
+#ifdef CONFIG_SPL_BUILD
.align 5
do_hang:
ldr sp, _TEXT_BASE /* use 32 words about stack */
bl hang /* hang and never return */
-#else /* !CONFIG_PRELOADER */
+#else /* !CONFIG_SPL_BUILD */
.align 5
undefined_instruction:
get_bad_stack
.align 5
.global arm1136_cache_flush
arm1136_cache_flush:
-#if !defined(CONFIG_SYS_NO_ICACHE)
+#if !defined(CONFIG_SYS_ICACHE_OFF)
mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
#endif
-#if !defined(CONFIG_SYS_NO_DCACHE)
+#if !defined(CONFIG_SYS_DCACHE_OFF)
mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache
#endif
mov pc, lr @ back to caller
-#endif /* CONFIG_PRELOADER */
+#endif /* CONFIG_SPL_BUILD */