mx31: provide readable WEIM CS accessor

[platform/kernel/u-boot.git] / arch / arm / cpu / arm1136 / mx31 / generic.c

diff --git a/arch/arm/cpu/arm1136/mx31/generic.c b/arch/arm/cpu/arm1136/mx31/generic.c
index cbe8243..78df7b9 100644 (file)
--- a/arch/arm/cpu/arm1136/mx31/generic.c
+++ b/arch/arm/cpu/arm1136/mx31/generic.c
@@ -22,15 +22,17 @@
  */
 
 #include <common.h>
-#include <asm/arch/mx31-regs.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/clock.h>
 #include <asm/io.h>
+#include <asm/arch/sys_proto.h>
 
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
 {
-       u32 mfi = (reg >> 10) & 0xf;
-       u32 mfn = reg & 0x3ff;
-       u32 mfd = (reg >> 16) & 0x3ff;
-       u32 pd =  (reg >> 26) & 0xf;
+       u32 mfi = GET_PLL_MFI(reg);
+       u32 mfn = GET_PLL_MFN(reg);
+       u32 mfd = GET_PLL_MFD(reg);
+       u32 pd =  GET_PLL_PD(reg);
 
        mfi = mfi <= 5 ? 5 : mfi;
        mfd += 1;
@@ -44,12 +46,12 @@ static u32 mx31_get_mpl_dpdgck_clk(void)
 {
        u32 infreq;
 
-       if ((__REG(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
+       if ((readl(CCM_CCMR) & CCMR_PRCS_MASK) == CCMR_FPM)
                infreq = CONFIG_MX31_CLK32 * 1024;
        else
                infreq = CONFIG_MX31_HCLK_FREQ;
 
-       return mx31_decode_pll(__REG(CCM_MPCTL), infreq);
+       return mx31_decode_pll(readl(CCM_MPCTL), infreq);
 }
 
 static u32 mx31_get_mcu_main_clk(void)
@@ -60,13 +62,24 @@ static u32 mx31_get_mcu_main_clk(void)
        return mx31_get_mpl_dpdgck_clk();
 }
 
-u32 mx31_get_ipg_clk(void)
+static u32 mx31_get_ipg_clk(void)
 {
        u32 freq = mx31_get_mcu_main_clk();
-       u32 pdr0 = __REG(CCM_PDR0);
+       u32 pdr0 = readl(CCM_PDR0);
 
-       freq /= ((pdr0 >> 3) & 0x7) + 1;
-       freq /= ((pdr0 >> 6) & 0x3) + 1;
+       freq /= GET_PDR0_MAX_PODF(pdr0) + 1;
+       freq /= GET_PDR0_IPG_PODF(pdr0) + 1;
+
+       return freq;
+}
+
+/* hsp is the clock for the ipu */
+static u32 mx31_get_hsp_clk(void)
+{
+       u32 freq = mx31_get_mcu_main_clk();
+       u32 pdr0 = readl(CCM_PDR0);
+
+       freq /= GET_PDR0_HSP_PODF(pdr0) + 1;
 
        return freq;
 }
@@ -76,6 +89,28 @@ void mx31_dump_clocks(void)
        u32 cpufreq = mx31_get_mcu_main_clk();
        printf("mx31 cpu clock: %dMHz\n",cpufreq / 1000000);
        printf("ipg clock     : %dHz\n", mx31_get_ipg_clk());
+       printf("hsp clock     : %dHz\n", mx31_get_hsp_clk());
+}
+
+unsigned int mxc_get_clock(enum mxc_clock clk)
+{
+       switch (clk) {
+       case MXC_ARM_CLK:
+               return mx31_get_mcu_main_clk();
+       case MXC_IPG_CLK:
+       case MXC_IPG_PERCLK:
+       case MXC_CSPI_CLK:
+       case MXC_UART_CLK:
+               return mx31_get_ipg_clk();
+       case MXC_IPU_CLK:
+               return mx31_get_hsp_clk();
+       }
+       return -1;
+}
+
+u32 imx_get_uartclk(void)
+{
+       return mxc_get_clock(MXC_UART_CLK);
 }
 
 void mx31_gpio_mux(unsigned long mode)
@@ -85,33 +120,96 @@ void mx31_gpio_mux(unsigned long mode)
        reg = IOMUXC_BASE + (mode & 0x1fc);
        shift = (~mode & 0x3) * 8;
 
-       tmp = __REG(reg);
+       tmp = readl(reg);
        tmp &= ~(0xff << shift);
        tmp |= ((mode >> IOMUX_MODE_POS) & 0xff) << shift;
-       __REG(reg) = tmp;
+       writel(tmp, reg);
 }
 
 void mx31_set_pad(enum iomux_pins pin, u32 config)
 {
-       u32 field, l;
-       void *reg;
+       u32 field, l, reg;
 
        pin &= IOMUX_PADNUM_MASK;
        reg = (IOMUXC_BASE + 0x154) + (pin + 2) / 3 * 4;
        field = (pin + 2) % 3;
 
-       l = __raw_readl(reg);
+       l = readl(reg);
        l &= ~(0x1ff << (field * 10));
        l |= config << (field * 10);
-       __raw_writel(l, reg);
+       writel(l, reg);
 
 }
 
+void mxc_setup_weimcs(int cs, const struct mxc_weimcs *weimcs)
+{
+       struct mx31_weim *weim = (struct mx31_weim *) WEIM_BASE;
+       struct mx31_weim_cscr *cscr = &weim->cscr[cs];
+
+       writel(weimcs->upper, &cscr->upper);
+       writel(weimcs->lower, &cscr->lower);
+       writel(weimcs->additional, &cscr->additional);
+}
+
+struct mx3_cpu_type mx31_cpu_type[] = {
+       { .srev = 0x00, .v = 0x10 },
+       { .srev = 0x10, .v = 0x11 },
+       { .srev = 0x11, .v = 0x11 },
+       { .srev = 0x12, .v = 0x1F },
+       { .srev = 0x13, .v = 0x1F },
+       { .srev = 0x14, .v = 0x12 },
+       { .srev = 0x15, .v = 0x12 },
+       { .srev = 0x28, .v = 0x20 },
+       { .srev = 0x29, .v = 0x20 },
+};
+
+u32 get_cpu_rev(void)
+{
+       u32 i, srev;
+
+       /* read SREV register from IIM module */
+       struct iim_regs *iim = (struct iim_regs *)MX31_IIM_BASE_ADDR;
+       srev = readl(&iim->iim_srev);
+
+       for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
+               if (srev == mx31_cpu_type[i].srev)
+                       return mx31_cpu_type[i].v;
+
+       return srev | 0x8000;
+}
+
+static char *get_reset_cause(void)
+{
+       /* read RCSR register from CCM module */
+       struct clock_control_regs *ccm =
+               (struct clock_control_regs *)CCM_BASE;
+
+       u32 cause = readl(&ccm->rcsr) & 0x07;
+
+       switch (cause) {
+       case 0x0000:
+               return "POR";
+       case 0x0001:
+               return "RST";
+       case 0x0002:
+               return "WDOG";
+       case 0x0006:
+               return "JTAG";
+       default:
+               return "unknown reset";
+       }
+}
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo (void)
 {
-       printf("CPU:   Freescale i.MX31 at %d MHz\n",
-               mx31_get_mcu_main_clk() / 1000000);
+       u32 srev = get_cpu_rev();
+
+       printf("CPU:   Freescale i.MX31 rev %d.%d%s at %d MHz.\n",
+                       (srev & 0xF0) >> 4, (srev & 0x0F),
+                       ((srev & 0x8000) ? " unknown" : ""),
+                       mx31_get_mcu_main_clk() / 1000000);
+       printf("Reset cause: %s\n", get_reset_cause());
        return 0;
 }
 #endif