Merge tag 'backport/v3.14.24-ltsi-rc1/phy-rcar-gen2-usb-to-v3.15' into backport/v3...
[platform/adaptation/renesas_rcar/renesas_kernel.git] / arch / arm / boot / dts / r8a7790.dtsi
index 495771b..d0e1773 100644 (file)
                spi2 = &msiof1;
                spi3 = &msiof2;
                spi4 = &msiof3;
+               vin0 = &vin0;
+               vin1 = &vin1;
+               vin2 = &vin2;
+               vin3 = &vin3;
        };
 
        cpus {
        };
 
        cmt0: timer@ffca0000 {
-               compatible = "renesas,cmt-48-gen2";
+               compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
                reg = <0 0xffca0000 0 0x1004>;
                interrupts = <0 142 IRQ_TYPE_LEVEL_HIGH>,
                             <0 143 IRQ_TYPE_LEVEL_HIGH>;
        };
 
        cmt1: timer@e6130000 {
-               compatible = "renesas,cmt-48-gen2";
+               compatible = "renesas,cmt-48-r8a7790", "renesas,cmt-48-gen2";
                reg = <0 0xe6130000 0 0x1004>;
                interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>,
                             <0 121 IRQ_TYPE_LEVEL_HIGH>,
                status = "disabled";
        };
 
+       vin0: video@e6ef0000 {
+               compatible = "renesas,vin-r8a7790";
+               clocks = <&mstp8_clks R8A7790_CLK_VIN0>;
+               reg = <0 0xe6ef0000 0 0x1000>;
+               interrupts = <0 188 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
+       vin1: video@e6ef1000 {
+               compatible = "renesas,vin-r8a7790";
+               clocks = <&mstp8_clks R8A7790_CLK_VIN1>;
+               reg = <0 0xe6ef1000 0 0x1000>;
+               interrupts = <0 189 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
+       vin2: video@e6ef2000 {
+               compatible = "renesas,vin-r8a7790";
+               clocks = <&mstp8_clks R8A7790_CLK_VIN2>;
+               reg = <0 0xe6ef2000 0 0x1000>;
+               interrupts = <0 190 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
+       vin3: video@e6ef3000 {
+               compatible = "renesas,vin-r8a7790";
+               clocks = <&mstp8_clks R8A7790_CLK_VIN3>;
+               reg = <0 0xe6ef3000 0 0x1000>;
+               interrupts = <0 191 IRQ_TYPE_LEVEL_HIGH>;
+               status = "disabled";
+       };
+
        clocks {
                #address-cells = <2>;
                #size-cells = <2>;
                mstp1_clks: mstp1_clks@e6150134 {
                        compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
                        reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
-                       clocks = <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
+                       clocks = <&m2_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
                                 <&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>,
                                 <&zs_clk>;
                        #clock-cells = <1>;
                        renesas,clock-indices = <
-                               R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
+                               R8A7790_CLK_JPU R8A7790_CLK_TMU1 R8A7790_CLK_TMU3 R8A7790_CLK_TMU2
                                R8A7790_CLK_CMT0 R8A7790_CLK_TMU0 R8A7790_CLK_VSP1_DU1
                                R8A7790_CLK_VSP1_DU0 R8A7790_CLK_VSP1_R R8A7790_CLK_VSP1_S
                        >;
                        clock-output-names =
-                               "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
+                               "jpu", "tmu1", "tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du1",
                                "vsp1-du0", "vsp1-rt", "vsp1-sy";
                };
                mstp2_clks: mstp2_clks@e6150138 {
 
        msiof0: spi@e6e20000 {
                compatible = "renesas,msiof-r8a7790";
-               reg = <0 0xe6e20000 0 0x0064>;
+               reg = <0 0xe6e20000 0 0x0064>, <0 0xe7e20000 0 0x0064>;
                interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp0_clks R8A7790_CLK_MSIOF0>;
+               dmas = <&dmac0 0x51>, <&dmac0 0x52>;
+               dma-names = "tx", "rx";
                #address-cells = <1>;
                #size-cells = <0>;
                status = "disabled";
 
        msiof1: spi@e6e10000 {
                compatible = "renesas,msiof-r8a7790";
-               reg = <0 0xe6e10000 0 0x0064>;
+               reg = <0 0xe6e10000 0 0x0064>, <0 0xe7e10000 0 0x0064>;
                interrupts = <0 157 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp2_clks R8A7790_CLK_MSIOF1>;
+               dmas = <&dmac0 0x55>, <&dmac0 0x56>;
+               dma-names = "tx", "rx";
                #address-cells = <1>;
                #size-cells = <0>;
                status = "disabled";
 
        msiof2: spi@e6e00000 {
                compatible = "renesas,msiof-r8a7790";
-               reg = <0 0xe6e00000 0 0x0064>;
+               reg = <0 0xe6e00000 0 0x0064>, <0 0xe7e00000 0 0x0064>;
                interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp2_clks R8A7790_CLK_MSIOF2>;
+               dmas = <&dmac0 0x41>, <&dmac0 0x42>;
+               dma-names = "tx", "rx";
                #address-cells = <1>;
                #size-cells = <0>;
                status = "disabled";
 
        msiof3: spi@e6c90000 {
                compatible = "renesas,msiof-r8a7790";
-               reg = <0 0xe6c90000 0 0x0064>;
+               reg = <0 0xe6c90000 0 0x0064>, <0 0xe7c90000 0 0x0064>;
                interrupts = <0 159 IRQ_TYPE_LEVEL_HIGH>;
                clocks = <&mstp2_clks R8A7790_CLK_MSIOF3>;
+               dmas = <&dmac0 0x45>, <&dmac0 0x46>;
+               dma-names = "tx", "rx";
                #address-cells = <1>;
                #size-cells = <0>;
                status = "disabled";
        rcar_sound: rcar_sound@0xec500000 {
                #sound-dai-cells = <1>;
                compatible =  "renesas,rcar_sound-r8a7790", "renesas,rcar_sound-gen2", "renesas,rcar_sound";
-               interrupt-parent = <&gic>;
                reg =   <0 0xec500000 0 0x1000>, /* SCU */
                        <0 0xec5a0000 0 0x100>,  /* ADG */
                        <0 0xec540000 0 0x1000>, /* SSIU */