Merge tag 'v3.14.25' into backport/v3.14.24-ltsi-rc1+v3.14.25/snapshot-merge.wip

[platform/adaptation/renesas_rcar/renesas_kernel.git] / arch / arm / boot / dts / r8a7779.dtsi

diff --git a/arch/arm/boot/dts/r8a7779.dtsi b/arch/arm/boot/dts/r8a7779.dtsi
index ddc8900..7cfba9a 100644 (file)
--- a/arch/arm/boot/dts/r8a7779.dtsi
+++ b/arch/arm/boot/dts/r8a7779.dtsi
@@ -261,7 +261,7 @@
        };
 
        tmu0: timer@ffd80000 {
-               compatible = "renesas,tmu";
+               compatible = "renesas,tmu-r8a7779", "renesas,tmu";
                reg = <0xffd80000 0x30>;
                interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
                             <0 33 IRQ_TYPE_LEVEL_HIGH>,
@@ -275,7 +275,7 @@
        };
 
        tmu1: timer@ffd81000 {
-               compatible = "renesas,tmu";
+               compatible = "renesas,tmu-r8a7779", "renesas,tmu";
                reg = <0xffd81000 0x30>;
                interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
                             <0 37 IRQ_TYPE_LEVEL_HIGH>,
@@ -289,7 +289,7 @@
        };
 
        tmu2: timer@ffd82000 {
-               compatible = "renesas,tmu";
+               compatible = "renesas,tmu-r8a7779", "renesas,tmu";
                reg = <0xffd82000 0x30>;
                interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
                             <0 41 IRQ_TYPE_LEVEL_HIGH>,
@@ -440,10 +440,10 @@
                /* Gate clocks */
                mstp0_clks: clocks@ffc80030 {
                        compatible = "renesas,r8a7779-mstp-clocks",
-                                    "renesas,cpg-mstp-clocks";
+                                    "renesas,cpg-mstp-clocks";
                        reg = <0xffc80030 4>;
                        clocks = <&cpg_clocks R8A7779_CLK_S>,
-                                <&cpg_clocks R8A7779_CLK_P>,
+                                <&cpg_clocks R8A7779_CLK_P>,
                                 <&cpg_clocks R8A7779_CLK_P>,
                                 <&cpg_clocks R8A7779_CLK_P>,
                                 <&cpg_clocks R8A7779_CLK_S>,
@@ -477,7 +477,7 @@
                };
                mstp1_clks: clocks@ffc80034 {
                        compatible = "renesas,r8a7779-mstp-clocks",
-                                    "renesas,cpg-mstp-clocks";
+                                    "renesas,cpg-mstp-clocks";
                        reg = <0xffc80034 4>, <0xffc80044 4>;
                        clocks = <&cpg_clocks R8A7779_CLK_P>,
                                 <&cpg_clocks R8A7779_CLK_P>,
@@ -506,7 +506,7 @@
                };
                mstp3_clks: clocks@ffc8003c {
                        compatible = "renesas,r8a7779-mstp-clocks",
-                                    "renesas,cpg-mstp-clocks";
+                                    "renesas,cpg-mstp-clocks";
                        reg = <0xffc8003c 4>;
                        clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>,
                                 <&s4_clk>, <&s4_clk>;