Merge tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

[platform/kernel/linux-rpi.git] / arch / arm / boot / dts / nspire / nspire.dtsi

diff --git a/arch/arm/boot/dts/nspire/nspire.dtsi b/arch/arm/boot/dts/nspire/nspire.dtsi
index 088bcc3..d56fef7 100644 (file)
--- a/arch/arm/boot/dts/nspire/nspire.dtsi
+++ b/arch/arm/boot/dts/nspire/nspire.dtsi
@@ -1,7 +1,5 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- *  linux/arch/arm/boot/nspire.dtsi
- *
  *  Copyright (C) 2013 Daniel Tang <tangrs@tangrs.id.au>
  */
 
@@ -11,8 +9,13 @@
        interrupt-parent = <&intc>;
 
        cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
                cpu@0 {
                        compatible = "arm,arm926ej-s";
+                       device_type = "cpu";
+                       reg = <0>;
                };
        };
 
@@ -21,8 +24,15 @@
        };
 
        sram: sram@a4000000 {
-               device = "memory";
-               reg = <0xa4000000 0x20000>;
+               compatible = "mmio-sram";
+               reg = <0xa4000000 0x20000>; /* 128k */
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges = <0 0xa4000000 0x20000>;
+
+               sram@0 {
+                       reg = <0x0 0x20000>;
+               };
        };
 
        timer_clk: timer_clk {
@@ -59,7 +69,6 @@
                compatible = "regulator-fixed";
 
                regulator-name = "USB VBUS output";
-               regulator-type = "voltage";
 
                regulator-min-microvolt = <5000000>;
                regulator-max-microvolt = <5000000>;
@@ -172,7 +181,14 @@
                        };
 
                        misc: misc@900a0000 {
+                               compatible = "ti,nspire-misc", "syscon", "simple-mfd";
                                reg = <0x900a0000 0x1000>;
+
+                               reboot {
+                                       compatible = "syscon-reboot";
+                                       offset = <0x08>;
+                                       value = <0x02>;
+                               };
                        };
 
                        pwr: pwr@900b0000 {