Merge tag 'u-boot-rockchip-20200501' of https://gitlab.denx.de/u-boot/custodians...

[platform/kernel/u-boot.git] / arch / arc / lib / start.S

diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S
index c78dd00..016ae85 100644 (file)
--- a/arch/arc/lib/start.S
+++ b/arch/arc/lib/start.S
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright (C) 2013-2014 Synopsys, Inc. All rights reserved.
- *
- * SPDX-License-Identifier:    GPL-2.0+
  */
 
 #include <asm-offsets.h>
@@ -17,7 +16,7 @@ ENTRY(_start)
        lr      r5, [ARC_BCR_IC_BUILD]
        breq    r5, 0, 1f               ; I$ doesn't exist
        lr      r5, [ARC_AUX_IC_CTRL]
-#ifndef CONFIG_SYS_ICACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_ICACHE_OFF)
        bclr    r5, r5, 0               ; 0 - Enable, 1 is Disable
 #else
        bset    r5, r5, 0               ; I$ exists, but is not used
@@ -38,7 +37,7 @@ ENTRY(_start)
        breq    r5, 0, 1f               ; D$ doesn't exist
        lr      r5, [ARC_AUX_DC_CTRL]
        bclr    r5, r5, 6               ; Invalidate (discard w/o wback)
-#ifndef CONFIG_SYS_DCACHE_OFF
+#if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
        bclr    r5, r5, 0               ; Enable (+Inv)
 #else
        bset    r5, r5, 0               ; Disable (+Inv)
@@ -62,6 +61,30 @@ ENTRY(_start)
 1:
 #endif
 
+#ifdef CONFIG_ISA_ARCV2
+       ; In case of DSP extension presence in HW some instructions
+       ; (related to integer multiply, multiply-accumulate, and divide
+       ; operation) executes on this DSP execution unit. So their
+       ; execution will depend on dsp configuration register (DSP_CTRL)
+       ; As we want these instructions to execute the same way regardless
+       ; of DSP presence we need to set DSP_CTRL properly.
+       lr      r5, [ARC_AUX_DSP_BUILD]
+       bmsk    r5, r5, 7
+       breq    r5, 0, 1f
+       mov     r5, 0
+       sr      r5, [ARC_AUX_DSP_CTRL]
+1:
+#endif
+
+#ifdef __ARC_UNALIGNED__
+       /*
+        * Enable handling of unaligned access in the CPU as by default
+        * this HW feature is disabled while GCC starting from 8.1.0
+        * unconditionally uses it for ARC HS cores.
+        */
+       flag    1 << STATUS_AD_BIT
+#endif
+
        /* Establish C runtime stack and frame */
        mov     %sp, CONFIG_SYS_INIT_SP_ADDR
        mov     %fp, %sp
@@ -76,6 +99,11 @@ ENTRY(_start)
        /* Initialize reserved area - note: r0 already contains address */
        bl      board_init_f_init_reserve
 
+#ifdef CONFIG_DEBUG_UART
+       /* Earliest point to set up early debug uart */
+       bl      debug_uart_init
+#endif
+
        /* Zero the one and only argument of "board_init_f" */
        mov_s   %r0, 0
        bl      board_init_f