-config CHAIN_OF_TRUST
+config NXP_ESBC
+ bool "NXP ESBC (secure boot) functionality"
+ help
+ Enable Freescale Secure Boot feature. Normally selected by defconfig.
+ If unsure, do not change.
+
+menu "Chain of trust / secure boot options"
depends on !FIT_SIGNATURE && NXP_ESBC
- imply CMD_BLOB
- imply CMD_HASH if ARM
+
+config CHAIN_OF_TRUST
select FSL_CAAM
select ARCH_MISC_INIT
+ select FSL_SEC_MON
select SPL_BOARD_INIT if (ARM && SPL)
select SPL_HASH if (ARM && SPL)
select SHA_HW_ACCEL
select SHA_PROG_HW_ACCEL
select ENV_IS_NOWHERE
+ select SYS_CPC_REINIT_F if MPC85xx && !SYS_RAMBOOT
select CMD_EXT4 if ARM
select CMD_EXT4_WRITE if ARM
- bool
- default y
+ imply CMD_BLOB
+ imply CMD_HASH if ARM
+ def_bool y
config CMD_ESBC_VALIDATE
bool "Enable the 'esbc_validate' and 'esbc_halt' commands"
- depends on CHAIN_OF_TRUST
default y
help
This option enables two commands used for secure booting:
help
For Layerscape based platforms, ESBC image Address in Header is 64bit.
+config SYS_FSL_SFP_BE
+ def_bool y
+ depends on PPC || FSL_LSCH2 || ARCH_LS1021A
+
+config SYS_FSL_SFP_LE
+ def_bool y
+ depends on !SYS_FSL_SFP_BE
+
+choice
+ prompt "SFP IP revision"
+ default SYS_FSL_SFP_VER_3_0 if PPC
+ default SYS_FSL_SFP_VER_3_4
+
+config SYS_FSL_SFP_VER_3_0
+ bool "SFP version 3.0"
+
+config SYS_FSL_SFP_VER_3_2
+ bool "SFP version 3.2"
+
+config SYS_FSL_SFP_VER_3_4
+ bool "SFP version 3.4"
+
+endchoice
+
+config SPL_UBOOT_KEY_HASH
+ string "Non-SRK key hash for U-Boot public/private key pair"
+ depends on SPL
+ default ""
+ help
+ Set the key hash for U-Boot here if public/private key pair used to
+ sign U-boot are different from the SRK hash put in the fuse. Example
+ of a key hash is
+ 41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
+ Otherwise leave this empty.
+
+if PPC
+
+config BOOTSCRIPT_COPY_RAM
+ bool "Secure boot copies boot script to RAM"
+ help
+ On systems that support chain of trust booting, a number of addresses
+ are required to set variables that are used in the copying and then
+ verification of different parts of the system. If enabled, the subsequent
+ options are for what location to use in each step.
+
+config BS_ADDR_DEVICE
+ hex "Address in RAM for bs_device"
+ depends on BOOTSCRIPT_COPY_RAM
+
+config BS_SIZE
+ hex "The size of bs_size which is the amount read from bs_device"
+ depends on BOOTSCRIPT_COPY_RAM
+
+config BS_ADDR_RAM
+ hex "Address in RAM for bs_ram"
+ depends on BOOTSCRIPT_COPY_RAM
+
+config BS_HDR_ADDR_DEVICE
+ hex "Address in RAM for bs_hdr_device"
+ depends on BOOTSCRIPT_COPY_RAM
+
+config BS_HDR_SIZE
+ hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
+ depends on BOOTSCRIPT_COPY_RAM
+
+config BS_HDR_ADDR_RAM
+ hex "Address in RAM for bs_hdr_ram"
+ depends on BOOTSCRIPT_COPY_RAM
+
+config BOOTSCRIPT_HDR_ADDR
+ hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
+ default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
+
+endif
+
+config SYS_FSL_SRK_LE
+ def_bool y
+ depends on ARM
+
+config KEY_REVOCATION
+ def_bool y
+
+endmenu
+
+comment "Other functionality shared between NXP SoCs"
+
config DEEP_SLEEP
bool "Enable SoC deep sleep feature"
depends on ARCH_T1024 || ARCH_T1040 || ARCH_T1042 || ARCH_LS1021A
Indicates this SoC supports deep sleep feature. If deep sleep is
supported, core will start to execute uboot when wakes up.
+config LAYERSCAPE_NS_ACCESS
+ bool "Layerscape non-secure access support"
+ depends on ARCH_LS1021A || FSL_LSCH2
+
+config PCIE1
+ bool "PCIe controller #1"
+ depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE2
+ bool "PCIe controller #2"
+ depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE3
+ bool "PCIe controller #3"
+ depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE4
+ bool "PCIe controller #4"
+ depends on LAYERSCAPE_NS_ACCESS || PPC
+
config FSL_USE_PCA9547_MUX
bool "Enable PCA9547 I2C Mux on Freescale boards"
depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3
endif
+config SYS_FSL_NUM_CC_PLLS
+ int "Number of clock control PLLs"
+ depends on MPC85xx || FSL_LSCH2 || FSL_LSCH3 || ARCH_LS1021A || ARCH_LS1028A
+ default 2 if ARCH_LS1021A || ARCH_LS1028A || FSL_LSCH2
+ default 6 if FSL_LSCH3 || MPC85xx
+
+config SYS_FSL_ESDHC_BE
+ bool
+
+config SYS_FSL_IFC_BE
+ bool
+
config FSL_QIXIS
bool "Enable QIXIS support"
depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3