41066b564c6ffcef40ccbc1e0a5d0d519604000c785d97bbefd25e4d288d1c8b.
Otherwise leave this empty.
+if PPC
+
+config BOOTSCRIPT_COPY_RAM
+ bool "Secure boot copies boot script to RAM"
+ help
+ On systems that support chain of trust booting, a number of addresses
+ are required to set variables that are used in the copying and then
+ verification of different parts of the system. If enabled, the subsequent
+ options are for what location to use in each step.
+
+config BS_ADDR_DEVICE
+ hex "Address in RAM for bs_device"
+ depends on BOOTSCRIPT_COPY_RAM
+
+config BS_SIZE
+ hex "The size of bs_size which is the amount read from bs_device"
+ depends on BOOTSCRIPT_COPY_RAM
+
+config BS_ADDR_RAM
+ hex "Address in RAM for bs_ram"
+ depends on BOOTSCRIPT_COPY_RAM
+
+config BS_HDR_ADDR_DEVICE
+ hex "Address in RAM for bs_hdr_device"
+ depends on BOOTSCRIPT_COPY_RAM
+
+config BS_HDR_SIZE
+ hex "The size of bs_hdr_size which is the amount read from bs_hdr_device"
+ depends on BOOTSCRIPT_COPY_RAM
+
+config BS_HDR_ADDR_RAM
+ hex "Address in RAM for bs_hdr_ram"
+ depends on BOOTSCRIPT_COPY_RAM
+
+config BOOTSCRIPT_HDR_ADDR
+ hex "CONFIG_BOOTSCRIPT_HDR_ADDR"
+ default BS_ADDR_RAM if BOOTSCRIPT_COPY_RAM
+
+endif
+
config SYS_FSL_SRK_LE
def_bool y
depends on ARM
Indicates this SoC supports deep sleep feature. If deep sleep is
supported, core will start to execute uboot when wakes up.
+config LAYERSCAPE_NS_ACCESS
+ bool "Layerscape non-secure access support"
+ depends on ARCH_LS1021A || FSL_LSCH2
+
+config PCIE1
+ bool "PCIe controller #1"
+ depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE2
+ bool "PCIe controller #2"
+ depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE3
+ bool "PCIe controller #3"
+ depends on LAYERSCAPE_NS_ACCESS || PPC
+
+config PCIE4
+ bool "PCIe controller #4"
+ depends on LAYERSCAPE_NS_ACCESS || PPC
+
config FSL_USE_PCA9547_MUX
bool "Enable PCA9547 I2C Mux on Freescale boards"
depends on PPC || ARCH_LS1021A || FSL_LSCH2 || FSL_LSCH3