bool "Nios II architecture"
select CPU
select DM
- imply DM_EVENT
+ select DM_EVENT
select OF_CONTROL
select SUPPORT_OF_CONTROL
imply CMD_DM
select SUPPORT_OF_CONTROL
select OF_CONTROL
select DM
- select SPL_SEPARATE_BSS if SPL
+ select DM_EVENT
+ imply SPL_SEPARATE_BSS if SPL
imply DM_SERIAL
- imply DM_ETH
- imply DM_EVENT
imply DM_MMC
imply DM_SPI
imply DM_SPI_FLASH
select BZIP2
select CMD_POWEROFF
select DM
+ select DM_EVENT
select DM_FUZZING_ENGINE
select DM_GPIO
select DM_I2C
select DM_SPI
select DM_SPI_FLASH
select GZIP_COMPRESSED
+ select IO_TRACE
select LZO
select OF_BOARD_SETUP
select PCI_ENDPOINT
imply CMD_IO
imply CMD_IOTRACE
imply CMD_LZMADEC
- imply CMD_SATA
imply CMD_SF
imply CMD_SF_TEST
imply CRC32_VERIFY
imply CMD_SF
imply CMD_SF_TEST
imply CMD_ZBOOT
- imply DM_ETH
- imply DM_EVENT
imply DM_GPIO
imply DM_KEYBOARD
imply DM_MMC
imply DM_SPI
imply DM_SPI_FLASH
imply DM_USB
- imply DM_VIDEO
+ imply VIDEO
imply SYSRESET
imply SPL_SYSRESET
imply SYSRESET_X86
Address for the Internal Memory-Mapped Registers (IMMR) window used
to configure the features of many Freescale / NXP SoCs.
-config SKIP_LOWLEVEL_INIT
- bool "Skip the calls to certain low level initialization functions"
+config MONITOR_IS_IN_RAM
+ bool "U-Boot is loaded in to RAM by a pre-loader"
+ depends on M68K || NIOS2
+
+menu "Skipping low level initialization functions"
depends on ARM || MIPS || RISCV
+
+config SKIP_LOWLEVEL_INIT
+ bool "Skip calls to certain low level initialization functions"
help
If enabled, then certain low level initializations (like setting up
the memory controller) are omitted and/or U-Boot does not relocate
debugger which performs these initializations itself.
config SPL_SKIP_LOWLEVEL_INIT
- bool "Skip the calls to certain low level initialization functions"
- depends on SPL && (ARM || MIPS || RISCV)
+ bool "Skip calls to certain low level initialization functions in SPL"
+ depends on SPL
help
If enabled, then certain low level initializations (like setting up
the memory controller) are omitted and/or U-Boot does not relocate
debugger which performs these initializations itself.
config TPL_SKIP_LOWLEVEL_INIT
- bool "Skip the calls to certain low level initialization functions"
+ bool "Skip calls to certain low level initialization functions in TPL"
depends on SPL && ARM
help
If enabled, then certain low level initializations (like setting up
debugger which performs these initializations itself.
config SKIP_LOWLEVEL_INIT_ONLY
- bool "Skip the call to lowlevel_init during early boot ONLY"
+ bool "Skip call to lowlevel_init during early boot ONLY"
depends on ARM
help
This allows just the call to lowlevel_init() to be skipped. The
performed.
config SPL_SKIP_LOWLEVEL_INIT_ONLY
- bool "Skip the call to lowlevel_init during early boot ONLY"
+ bool "Skip call to lowlevel_init during early SPL boot ONLY"
depends on SPL && ARM
help
This allows just the call to lowlevel_init() to be skipped. The
performed.
config TPL_SKIP_LOWLEVEL_INIT_ONLY
- bool "Skip the call to lowlevel_init during early boot ONLY"
+ bool "Skip call to lowlevel_init during early TPL boot ONLY"
depends on TPL && ARM
help
This allows just the call to lowlevel_init() to be skipped. The
normal CP15 init (such as enabling the instruction cache) is still
performed.
+endmenu
+
+config SYS_HAS_NONCACHED_MEMORY
+ bool "Enable reserving a non-cached memory area for drivers"
+ depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH)
+ help
+ This is useful for drivers that would otherwise require a lot of
+ explicit cache maintenance. For some drivers it's also impossible to
+ properly maintain the cache. For example if the regions that need to
+ be flushed are not a multiple of the cache-line size, *and* padding
+ cannot be allocated between the regions to align them (i.e. if the
+ HW requires a contiguous array of regions, and the size of each
+ region is not cache-aligned), then a flush of one region may result
+ in overwriting data that hardware has written to another region in
+ the same cache-line. This can happen for example in network drivers
+ where descriptors for buffers are typically smaller than the CPU
+ cache-line (e.g. 16 bytes vs. 32 or 64 bytes).
+
+config SYS_NONCACHED_MEMORY
+ hex "Size in bytes of the non-cached memory area"
+ depends on SYS_HAS_NONCACHED_MEMORY
+ default 0x100000
+ help
+ Size of non-cached memory area. This area of memory will be typically
+ located right below the malloc() area and mapped uncached in the MMU.
+
source "arch/arc/Kconfig"
source "arch/arm/Kconfig"
source "arch/m68k/Kconfig"
projects / platform / kernel / u-boot.git / blobdiff